FR2808333B1 - Procede et appareil de calibrage pour corriger des erreurs de synchronisation de largeur d'impulsion lors de tests de circuits integres - Google Patents

Procede et appareil de calibrage pour corriger des erreurs de synchronisation de largeur d'impulsion lors de tests de circuits integres

Info

Publication number
FR2808333B1
FR2808333B1 FR0103388A FR0103388A FR2808333B1 FR 2808333 B1 FR2808333 B1 FR 2808333B1 FR 0103388 A FR0103388 A FR 0103388A FR 0103388 A FR0103388 A FR 0103388A FR 2808333 B1 FR2808333 B1 FR 2808333B1
Authority
FR
France
Prior art keywords
event
pulse width
data
integrated circuit
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0103388A
Other languages
English (en)
Other versions
FR2808333A1 (fr
Inventor
Joseph C Helland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Schlumberger Technologies Inc
Original Assignee
Schlumberger Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Schlumberger Technologies Inc filed Critical Schlumberger Technologies Inc
Publication of FR2808333A1 publication Critical patent/FR2808333A1/fr
Application granted granted Critical
Publication of FR2808333B1 publication Critical patent/FR2808333B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
FR0103388A 2000-03-15 2001-03-13 Procede et appareil de calibrage pour corriger des erreurs de synchronisation de largeur d'impulsion lors de tests de circuits integres Expired - Fee Related FR2808333B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/526,407 US6496953B1 (en) 2000-03-15 2000-03-15 Calibration method and apparatus for correcting pulse width timing errors in integrated circuit testing

Publications (2)

Publication Number Publication Date
FR2808333A1 FR2808333A1 (fr) 2001-11-02
FR2808333B1 true FR2808333B1 (fr) 2004-08-20

Family

ID=24097209

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0103388A Expired - Fee Related FR2808333B1 (fr) 2000-03-15 2001-03-13 Procede et appareil de calibrage pour corriger des erreurs de synchronisation de largeur d'impulsion lors de tests de circuits integres

Country Status (6)

Country Link
US (1) US6496953B1 (fr)
JP (1) JP2001305197A (fr)
KR (1) KR20010092312A (fr)
DE (1) DE10112311A1 (fr)
FR (1) FR2808333B1 (fr)
TW (1) TW508446B (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6985840B1 (en) * 2000-07-31 2006-01-10 Novas Software, Inc. Circuit property verification system
US20030099139A1 (en) * 2001-08-24 2003-05-29 Abrosimov Igor Anatolievich Memory test apparatus and method of testing
US7089135B2 (en) * 2002-05-20 2006-08-08 Advantest Corp. Event based IC test system
US7810005B1 (en) * 2006-11-01 2010-10-05 Credence Systems Corporation Method and system for correcting timing errors in high data rate automated test equipment
RU2363093C1 (ru) * 2008-02-11 2009-07-27 Федеральное Государственное Образовательное Учреждение Высшего Профессионального Образования "Южный Федеральный Университет" Устройство для контроля временных рассогласований импульсных последовательностей
US7904755B2 (en) * 2008-05-30 2011-03-08 Infineon Technologies Ag Embedded software testing using a single output
US8683164B2 (en) 2009-02-04 2014-03-25 Micron Technology, Inc. Stacked-die memory systems and methods for training stacked-die memory systems
US8310885B2 (en) 2010-04-28 2012-11-13 International Business Machines Corporation Measuring SDRAM control signal timing

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225772A (en) 1990-09-05 1993-07-06 Schlumberger Technologies, Inc. Automatic test equipment system using pin slice architecture
US5212443A (en) 1990-09-05 1993-05-18 Schlumberger Technologies, Inc. Event sequencer for automatic test equipment
US6060898A (en) * 1997-09-30 2000-05-09 Credence Systems Corporation Format sensitive timing calibration for an integrated circuit tester
US6360343B1 (en) * 1999-02-26 2002-03-19 Advantest Corp. Delta time event based test system

Also Published As

Publication number Publication date
FR2808333A1 (fr) 2001-11-02
US6496953B1 (en) 2002-12-17
KR20010092312A (ko) 2001-10-24
JP2001305197A (ja) 2001-10-31
TW508446B (en) 2002-11-01
DE10112311A1 (de) 2002-01-17

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Legal Events

Date Code Title Description
CD Change of name or company name
TP Transmission of property
TP Transmission of property
ST Notification of lapse

Effective date: 20081125

TP Transmission of property