FR2852465B1 - Generateur d'horloge - Google Patents

Generateur d'horloge

Info

Publication number
FR2852465B1
FR2852465B1 FR0303111A FR0303111A FR2852465B1 FR 2852465 B1 FR2852465 B1 FR 2852465B1 FR 0303111 A FR0303111 A FR 0303111A FR 0303111 A FR0303111 A FR 0303111A FR 2852465 B1 FR2852465 B1 FR 2852465B1
Authority
FR
France
Prior art keywords
clock generator
clock
generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0303111A
Other languages
English (en)
Other versions
FR2852465A1 (fr
Inventor
David Ruffieux
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSEM Centre Suisse dElectronique et de Microtechnique SA Recherche et Développement
Original Assignee
CSEM Centre Suisse dElectronique et de Microtechnique SA Recherche et Développement
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSEM Centre Suisse dElectronique et de Microtechnique SA Recherche et Développement filed Critical CSEM Centre Suisse dElectronique et de Microtechnique SA Recherche et Développement
Priority to FR0303111A priority Critical patent/FR2852465B1/fr
Priority to EP04716530A priority patent/EP1606877A1/fr
Priority to PCT/CH2004/000121 priority patent/WO2004082141A1/fr
Priority to US10/548,806 priority patent/US7339854B2/en
Publication of FR2852465A1 publication Critical patent/FR2852465A1/fr
Application granted granted Critical
Publication of FR2852465B1 publication Critical patent/FR2852465B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L5/00—Automatic control of voltage, current, or power
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00032—DC control of switching transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Electric Clocks (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
FR0303111A 2003-03-13 2003-03-13 Generateur d'horloge Expired - Fee Related FR2852465B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR0303111A FR2852465B1 (fr) 2003-03-13 2003-03-13 Generateur d'horloge
EP04716530A EP1606877A1 (fr) 2003-03-13 2004-03-03 Générateur d'horloge
PCT/CH2004/000121 WO2004082141A1 (fr) 2003-03-13 2004-03-03 Générateur d'horloge
US10/548,806 US7339854B2 (en) 2003-03-13 2004-03-03 Clock generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0303111A FR2852465B1 (fr) 2003-03-13 2003-03-13 Generateur d'horloge

Publications (2)

Publication Number Publication Date
FR2852465A1 FR2852465A1 (fr) 2004-09-17
FR2852465B1 true FR2852465B1 (fr) 2005-04-29

Family

ID=32893273

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0303111A Expired - Fee Related FR2852465B1 (fr) 2003-03-13 2003-03-13 Generateur d'horloge

Country Status (4)

Country Link
US (1) US7339854B2 (fr)
EP (1) EP1606877A1 (fr)
FR (1) FR2852465B1 (fr)
WO (1) WO2004082141A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2416968A (en) * 2004-07-30 2006-02-08 Hewlett Packard Development Co Clock circuit for RFID tag which forces a change in oscillator state in response to transition in received signal to achieve immediate synchronisation
CN115225065A (zh) * 2022-08-31 2022-10-21 上海韬润半导体有限公司 时钟调整电路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63290046A (ja) * 1987-05-21 1988-11-28 Pioneer Electronic Corp パルス幅ひずみ補正回路
JPH07114349B2 (ja) * 1988-12-28 1995-12-06 株式会社東芝 デューティ制御回路装置
US4959557A (en) * 1989-05-18 1990-09-25 Compaq Computer Corporation Negative feedback circuit to control the duty cycle of a logic system clock
US5345186A (en) * 1993-01-19 1994-09-06 Credence Systems Corporation Retriggered oscillator for jitter-free phase locked loop frequency synthesis
US5477180A (en) * 1994-10-11 1995-12-19 At&T Global Information Solutions Company Circuit and method for generating a clock signal
GB9522223D0 (en) * 1995-10-31 1996-01-03 Sgs Thomson Microelectronics A circuit for generating an output signal having a 50% duty cycle
US5907254A (en) * 1996-02-05 1999-05-25 Chang; Theodore H. Reshaping periodic waveforms to a selected duty cycle
US5912574A (en) * 1996-12-09 1999-06-15 Sun Microsystems, Inc. Dual loop PLL with secondary loop to achieve 50% duty cycle
US6028491A (en) * 1998-04-29 2000-02-22 Atmel Corporation Crystal oscillator with controlled duty cycle
US6320438B1 (en) * 2000-08-17 2001-11-20 Pericom Semiconductor Corp. Duty-cycle correction driver with dual-filter feedback loop
US6509771B1 (en) * 2001-12-14 2003-01-21 International Business Machines Corporation Enhanced operational frequency for a precise and programmable duty cycle generator

Also Published As

Publication number Publication date
US20060214701A1 (en) 2006-09-28
US7339854B2 (en) 2008-03-04
EP1606877A1 (fr) 2005-12-21
WO2004082141A1 (fr) 2004-09-23
FR2852465A1 (fr) 2004-09-17

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20091130