FR2860919B1 - Structures et procedes de fabrication de regions semiconductrices sur isolant - Google Patents

Structures et procedes de fabrication de regions semiconductrices sur isolant

Info

Publication number
FR2860919B1
FR2860919B1 FR0350665A FR0350665A FR2860919B1 FR 2860919 B1 FR2860919 B1 FR 2860919B1 FR 0350665 A FR0350665 A FR 0350665A FR 0350665 A FR0350665 A FR 0350665A FR 2860919 B1 FR2860919 B1 FR 2860919B1
Authority
FR
France
Prior art keywords
insulation
structures
methods
semiconductor regions
producing semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0350665A
Other languages
English (en)
Other versions
FR2860919A1 (fr
Inventor
Stephane Monfray
Aomar Halimaoui
Philippe Coronel
Damien Lenoble
Beranger Claire Fenouillet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, STMicroelectronics SA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR0350665A priority Critical patent/FR2860919B1/fr
Priority to US10/960,436 priority patent/US20050085026A1/en
Publication of FR2860919A1 publication Critical patent/FR2860919A1/fr
Priority to US11/713,553 priority patent/US7638844B2/en
Application granted granted Critical
Publication of FR2860919B1 publication Critical patent/FR2860919B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
FR0350665A 2003-10-09 2003-10-09 Structures et procedes de fabrication de regions semiconductrices sur isolant Expired - Fee Related FR2860919B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR0350665A FR2860919B1 (fr) 2003-10-09 2003-10-09 Structures et procedes de fabrication de regions semiconductrices sur isolant
US10/960,436 US20050085026A1 (en) 2003-10-09 2004-10-07 Manufacturing method of semiconductor-on-insulator region structures
US11/713,553 US7638844B2 (en) 2003-10-09 2007-03-02 Manufacturing method of semiconductor-on-insulator region structures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0350665A FR2860919B1 (fr) 2003-10-09 2003-10-09 Structures et procedes de fabrication de regions semiconductrices sur isolant

Publications (2)

Publication Number Publication Date
FR2860919A1 FR2860919A1 (fr) 2005-04-15
FR2860919B1 true FR2860919B1 (fr) 2009-09-11

Family

ID=34355514

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0350665A Expired - Fee Related FR2860919B1 (fr) 2003-10-09 2003-10-09 Structures et procedes de fabrication de regions semiconductrices sur isolant

Country Status (2)

Country Link
US (2) US20050085026A1 (fr)
FR (1) FR2860919B1 (fr)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1727194A1 (fr) * 2005-05-27 2006-11-29 Interuniversitair Microelektronica Centrum vzw ( IMEC) Méthode de formation de motif par topographie haute résolution
US8557668B2 (en) * 2012-01-12 2013-10-15 Globalfoundries Singapore Pte. Ltd. Method for forming N-shaped bottom stress liner
CN106610561B (zh) * 2015-10-20 2020-03-24 无锡华润上华科技有限公司 光刻版的形成方法
WO2019195428A1 (fr) 2018-04-04 2019-10-10 Qorvo Us, Inc. Module à base de nitrure de gallium à performance électrique améliorée et son procédé de fabrication
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US12165951B2 (en) 2018-07-02 2024-12-10 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
EP3915134A1 (fr) 2019-01-23 2021-12-01 Qorvo US, Inc. Dispositif semiconducteur radiofréquence et son procédé de fabrication
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
CN116583949A (zh) 2020-12-11 2023-08-11 Qorvo美国公司 多级3d堆叠式封装和其形成方法
US12062571B2 (en) 2021-03-05 2024-08-13 Qorvo Us, Inc. Selective etching process for SiGe and doped epitaxial silicon

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897703A (en) * 1988-01-29 1990-01-30 Texas Instruments Incorporated Recessed contact bipolar transistor and method
NL8800847A (nl) * 1988-04-05 1989-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een soi-struktuur.
EP0810652B1 (fr) * 1992-01-28 2003-05-07 Canon Kabushiki Kaisha Dispositif semi-conducteur
KR0142797B1 (ko) * 1994-06-17 1998-08-17 문정환 실리콘-온-인슐레이터구조의 제조방법
KR20000045305A (ko) * 1998-12-30 2000-07-15 김영환 완전 공핍형 에스·오·아이 소자 및 그 제조방법
US6355493B1 (en) * 1999-07-07 2002-03-12 Silicon Wafer Technologies Inc. Method for forming IC's comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon
US6562666B1 (en) * 2000-10-31 2003-05-13 International Business Machines Corporation Integrated circuits with reduced substrate capacitance
FR2821483B1 (fr) * 2001-02-28 2004-07-09 St Microelectronics Sa Procede de fabrication d'un transistor a grille isolee et a architecture du type substrat sur isolant, et transistor correspondant
US6611023B1 (en) * 2001-05-01 2003-08-26 Advanced Micro Devices, Inc. Field effect transistor with self alligned double gate and method of forming same

Also Published As

Publication number Publication date
FR2860919A1 (fr) 2005-04-15
US20050085026A1 (en) 2005-04-21
US20080087959A1 (en) 2008-04-17
US7638844B2 (en) 2009-12-29

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