FR2887367B1 - Procede de maintien de la contrainte dans un ilot grave dans une couche mince contrainte et structure obtenue par la mise en oeuvre du procede - Google Patents

Procede de maintien de la contrainte dans un ilot grave dans une couche mince contrainte et structure obtenue par la mise en oeuvre du procede

Info

Publication number
FR2887367B1
FR2887367B1 FR0506047A FR0506047A FR2887367B1 FR 2887367 B1 FR2887367 B1 FR 2887367B1 FR 0506047 A FR0506047 A FR 0506047A FR 0506047 A FR0506047 A FR 0506047A FR 2887367 B1 FR2887367 B1 FR 2887367B1
Authority
FR
France
Prior art keywords
island
serious
stress
maintaining
carrying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0506047A
Other languages
English (en)
Other versions
FR2887367A1 (fr
Inventor
Amice Boussagol
Ian Cayrefourcq
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0506047A priority Critical patent/FR2887367B1/fr
Priority to US11/214,590 priority patent/US20060284252A1/en
Priority to PCT/EP2006/063171 priority patent/WO2006134119A1/fr
Priority to TW095121111A priority patent/TW200710974A/zh
Publication of FR2887367A1 publication Critical patent/FR2887367A1/fr
Application granted granted Critical
Publication of FR2887367B1 publication Critical patent/FR2887367B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3238—Materials thereof being insulating materials
FR0506047A 2005-06-15 2005-06-15 Procede de maintien de la contrainte dans un ilot grave dans une couche mince contrainte et structure obtenue par la mise en oeuvre du procede Expired - Fee Related FR2887367B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR0506047A FR2887367B1 (fr) 2005-06-15 2005-06-15 Procede de maintien de la contrainte dans un ilot grave dans une couche mince contrainte et structure obtenue par la mise en oeuvre du procede
US11/214,590 US20060284252A1 (en) 2005-06-15 2005-08-29 Process for holding strain in an island etched in a strained thin layer and structure obtained by implementation of this process
PCT/EP2006/063171 WO2006134119A1 (fr) 2005-06-15 2006-06-13 Procede de maintien de la contrainte dans un ilot grave dans une couche mince contrainte et structure obtenue par la mise en oeuvre du procede
TW095121111A TW200710974A (en) 2005-06-15 2006-06-14 Process for holding strain in an island etched in a strained thin layer and structure obtained by implementation of this process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0506047A FR2887367B1 (fr) 2005-06-15 2005-06-15 Procede de maintien de la contrainte dans un ilot grave dans une couche mince contrainte et structure obtenue par la mise en oeuvre du procede

Publications (2)

Publication Number Publication Date
FR2887367A1 FR2887367A1 (fr) 2006-12-22
FR2887367B1 true FR2887367B1 (fr) 2008-06-27

Family

ID=36001048

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0506047A Expired - Fee Related FR2887367B1 (fr) 2005-06-15 2005-06-15 Procede de maintien de la contrainte dans un ilot grave dans une couche mince contrainte et structure obtenue par la mise en oeuvre du procede

Country Status (4)

Country Link
US (1) US20060284252A1 (fr)
FR (1) FR2887367B1 (fr)
TW (1) TW200710974A (fr)
WO (1) WO2006134119A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008044983B4 (de) * 2008-08-29 2014-08-21 Advanced Micro Devices, Inc. Verfahren zum Herstellen eines strukturierten verformten Substrats, insbesondere zur Herstellung verformter Transistoren mit geringerer Dicke der aktiven Schicht
WO2010022972A1 (fr) * 2008-08-29 2010-03-04 Advanced Micro Devices Inc. Substrat contraint structuré pour former des transistors contraints à épaisseur réduite de la couche active
FR2986369B1 (fr) * 2012-01-30 2016-12-02 Commissariat Energie Atomique Procede pour contraindre un motif mince et procede de fabrication de transistor integrant ledit procede
WO2020150482A1 (fr) * 2019-01-16 2020-07-23 The Regents Of The University Of California Liaison de tranche pour incorporer des régions actives avec des nanocaractéristiques relaxées

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225368A (en) * 1991-02-08 1993-07-06 The United States Of America As Represented By The United States Department Of Energy Method of producing strained-layer semiconductor devices via subsurface-patterning
US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6900103B2 (en) * 2001-03-02 2005-05-31 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6646322B2 (en) * 2001-03-02 2003-11-11 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
JP4136939B2 (ja) * 2002-01-09 2008-08-20 松下電器産業株式会社 半導体装置およびその製造方法
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
JP4949628B2 (ja) * 2002-10-30 2012-06-13 台湾積體電路製造股▲ふん▼有限公司 Ｃｍｏｓプロセス中に歪み半導基板層を保護する方法
US7238588B2 (en) * 2003-01-14 2007-07-03 Advanced Micro Devices, Inc. Silicon buffered shallow trench isolation
US6960781B2 (en) * 2003-03-07 2005-11-01 Amberwave Systems Corporation Shallow trench isolation process
US6991998B2 (en) * 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7067400B2 (en) * 2004-09-17 2006-06-27 International Business Machines Corporation Method for preventing sidewall consumption during oxidation of SGOI islands

Also Published As

Publication number Publication date
WO2006134119A1 (fr) 2006-12-21
FR2887367A1 (fr) 2006-12-22
US20060284252A1 (en) 2006-12-21
TW200710974A (en) 2007-03-16

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Effective date: 20100226