FR2905209B1 - Procede et dispositif de decodage de blocs encodes avec un code ldpc - Google Patents

Procede et dispositif de decodage de blocs encodes avec un code ldpc

Info

Publication number
FR2905209B1
FR2905209B1 FR0607489A FR0607489A FR2905209B1 FR 2905209 B1 FR2905209 B1 FR 2905209B1 FR 0607489 A FR0607489 A FR 0607489A FR 0607489 A FR0607489 A FR 0607489A FR 2905209 B1 FR2905209 B1 FR 2905209B1
Authority
FR
France
Prior art keywords
ldpc code
decoding blocks
blocks encoded
encoded
decoding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0607489A
Other languages
English (en)
Other versions
FR2905209A1 (fr
Inventor
Vincent Heinrich
Pascal Urard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0607489A priority Critical patent/FR2905209B1/fr
Priority to US11/834,198 priority patent/US8046658B2/en
Publication of FR2905209A1 publication Critical patent/FR2905209A1/fr
Application granted granted Critical
Publication of FR2905209B1 publication Critical patent/FR2905209B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H03M13/6505—Memory efficient implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6566—Implementations concerning memory access contentions

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Error Detection And Correction (AREA)
FR0607489A 2006-08-24 2006-08-24 Procede et dispositif de decodage de blocs encodes avec un code ldpc Expired - Fee Related FR2905209B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0607489A FR2905209B1 (fr) 2006-08-24 2006-08-24 Procede et dispositif de decodage de blocs encodes avec un code ldpc
US11/834,198 US8046658B2 (en) 2006-08-24 2007-08-06 Method and device for decoding blocks encoded with an LDPC code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0607489A FR2905209B1 (fr) 2006-08-24 2006-08-24 Procede et dispositif de decodage de blocs encodes avec un code ldpc

Publications (2)

Publication Number Publication Date
FR2905209A1 FR2905209A1 (fr) 2008-02-29
FR2905209B1 true FR2905209B1 (fr) 2008-10-31

Family

ID=37694583

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0607489A Expired - Fee Related FR2905209B1 (fr) 2006-08-24 2006-08-24 Procede et dispositif de decodage de blocs encodes avec un code ldpc

Country Status (2)

Country Link
US (1) US8046658B2 (fr)
FR (1) FR2905209B1 (fr)

Families Citing this family (15)

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WO2007075106A1 (fr) * 2005-12-29 2007-07-05 Intel Corporation Codeur de code de verification de parite faible densite rapide
RU2437237C1 (ru) * 2007-09-28 2011-12-20 ЭлДжи ЭЛЕКТРОНИКС ИНК. Устройство для передачи и приема сигнала и способ передачи и приема сигнала
WO2010019169A1 (fr) * 2008-08-15 2010-02-18 Lsi Corporation Décodage de liste de mots codés proches dans une mémoire rom
KR101473046B1 (ko) * 2009-03-05 2014-12-15 엘에스아이 코포레이션 반복 복호기들을 위한 개선된 터보-등화 방법들
CN102077173B (zh) 2009-04-21 2015-06-24 艾格瑞系统有限责任公司 利用写入验证减轻代码的误码平层
US8464142B2 (en) 2010-04-23 2013-06-11 Lsi Corporation Error-correction decoder employing extrinsic message averaging
US8499226B2 (en) 2010-06-29 2013-07-30 Lsi Corporation Multi-mode layered decoding
US8458555B2 (en) 2010-06-30 2013-06-04 Lsi Corporation Breaking trapping sets using targeted bit adjustment
US8504900B2 (en) 2010-07-02 2013-08-06 Lsi Corporation On-line discovery and filtering of trapping sets
US8989252B1 (en) * 2011-01-19 2015-03-24 Marvell International Ltd. Methods and apparatus for power efficient iterative equalization
US8768990B2 (en) 2011-11-11 2014-07-01 Lsi Corporation Reconfigurable cyclic shifter arrangement
RU2012146685A (ru) 2012-11-01 2014-05-10 ЭлЭсАй Корпорейшн База данных наборов-ловушек для декодера на основе разреженного контроля четности
US8930790B1 (en) 2013-09-13 2015-01-06 U-Blox Ag Method and apparatus for identifying selected values from among a set of values
RU2573243C2 (ru) 2013-10-28 2016-01-20 Общество с ограниченной ответственностью "Топкон Позишионинг Системс" Способ и устройство для измерения текущего отношения сигнал/шум при декодировании ldpc-кодов (варианты)
KR102254102B1 (ko) * 2015-01-23 2021-05-20 삼성전자주식회사 메모리 시스템 및 메모리 시스템의 동작 방법

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7159170B2 (en) * 2003-06-13 2007-01-02 Broadcom Corporation LDPC (low density parity check) coded modulation symbol decoding
JP2005093038A (ja) * 2003-09-19 2005-04-07 Fujitsu Ltd 記録再生装置および記録再生回路
US7484158B2 (en) * 2003-12-03 2009-01-27 Infineon Technologies Ag Method for decoding a low-density parity check (LDPC) codeword
US7174495B2 (en) * 2003-12-19 2007-02-06 Emmanuel Boutillon LDPC decoder, corresponding method, system and computer program
KR100594818B1 (ko) * 2004-04-13 2006-07-03 한국전자통신연구원 순차적 복호를 이용한 저밀도 패리티 검사 부호의 복호장치 및 그 방법
JP4050726B2 (ja) * 2004-06-23 2008-02-20 株式会社東芝 復号装置
US7260762B2 (en) * 2004-07-26 2007-08-21 Motorola, Inc. Decoder performance for block product codes
WO2006020934A2 (fr) * 2004-08-13 2006-02-23 Conexant Systems, Inc. Systemes et procedes permettant de reduire le temps d'attente dans un systeme de transmission numerique
US20060085720A1 (en) * 2004-10-04 2006-04-20 Hau Thien Tran Message passing memory and barrel shifter arrangement in LDPC (Low Density Parity Check) decoder supporting multiple LDPC codes
US7760880B2 (en) * 2004-10-13 2010-07-20 Viasat, Inc. Decoder architecture system and method
US7577892B1 (en) * 2005-08-25 2009-08-18 Marvell International Ltd High speed iterative decoder
US7770090B1 (en) * 2005-09-14 2010-08-03 Trident Microsystems (Far East) Ltd. Efficient decoders for LDPC codes
US7707479B2 (en) * 2005-12-13 2010-04-27 Samsung Electronics Co., Ltd. Method of generating structured irregular low density parity checkcodes for wireless systems
US7669106B1 (en) * 2006-04-17 2010-02-23 Aquantia Corporation Optimization of low density parity check (LDPC) building blocks using multi-input Gilbert cells

Also Published As

Publication number Publication date
US8046658B2 (en) 2011-10-25
FR2905209A1 (fr) 2008-02-29
US20080052596A1 (en) 2008-02-28

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Legal Events

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Effective date: 20130430