FR2935539B1 - Circuit cmos tridimensionnel sur deux substrats desalignes et procede de realisation - Google Patents

Circuit cmos tridimensionnel sur deux substrats desalignes et procede de realisation

Info

Publication number
FR2935539B1
FR2935539B1 FR0804689A FR0804689A FR2935539B1 FR 2935539 B1 FR2935539 B1 FR 2935539B1 FR 0804689 A FR0804689 A FR 0804689A FR 0804689 A FR0804689 A FR 0804689A FR 2935539 B1 FR2935539 B1 FR 2935539B1
Authority
FR
France
Prior art keywords
desaligned
substrates
cmos circuit
making same
dimensional cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0804689A
Other languages
English (en)
Other versions
FR2935539A1 (fr
Inventor
Benjamin Vincent
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR0804689A priority Critical patent/FR2935539B1/fr
Priority to EP09809280A priority patent/EP2319080A1/fr
Priority to PCT/EP2009/005795 priority patent/WO2010022856A1/fr
Priority to US13/059,483 priority patent/US8569801B2/en
Publication of FR2935539A1 publication Critical patent/FR2935539A1/fr
Application granted granted Critical
Publication of FR2935539B1 publication Critical patent/FR2935539B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
FR0804689A 2008-08-26 2008-08-26 Circuit cmos tridimensionnel sur deux substrats desalignes et procede de realisation Expired - Fee Related FR2935539B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR0804689A FR2935539B1 (fr) 2008-08-26 2008-08-26 Circuit cmos tridimensionnel sur deux substrats desalignes et procede de realisation
EP09809280A EP2319080A1 (fr) 2008-08-26 2009-08-10 Circuit cmos tridimensionnel sur deux substrats désalignés et procédé de réalisation
PCT/EP2009/005795 WO2010022856A1 (fr) 2008-08-26 2009-08-10 Circuit cmos tridimensionnel sur deux substrats désalignés et procédé de réalisation
US13/059,483 US8569801B2 (en) 2008-08-26 2009-08-10 Three-dimensional CMOS circuit on two offset substrates and method for making same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0804689A FR2935539B1 (fr) 2008-08-26 2008-08-26 Circuit cmos tridimensionnel sur deux substrats desalignes et procede de realisation

Publications (2)

Publication Number Publication Date
FR2935539A1 FR2935539A1 (fr) 2010-03-05
FR2935539B1 true FR2935539B1 (fr) 2010-12-10

Family

ID=40429980

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0804689A Expired - Fee Related FR2935539B1 (fr) 2008-08-26 2008-08-26 Circuit cmos tridimensionnel sur deux substrats desalignes et procede de realisation

Country Status (4)

Country Link
US (1) US8569801B2 (fr)
EP (1) EP2319080A1 (fr)
FR (1) FR2935539B1 (fr)
WO (1) WO2010022856A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2935539B1 (fr) * 2008-08-26 2010-12-10 Commissariat Energie Atomique Circuit cmos tridimensionnel sur deux substrats desalignes et procede de realisation
US11670677B2 (en) 2020-10-02 2023-06-06 Samsung Electronics Co., Ltd. Crossing multi-stack nanosheet structure and method of manufacturing the same

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3038939B2 (ja) * 1991-02-08 2000-05-08 日産自動車株式会社 半導体装置
JP3017860B2 (ja) * 1991-10-01 2000-03-13 株式会社東芝 半導体基体およびその製造方法とその半導体基体を用いた半導体装置
JP4318768B2 (ja) * 1997-07-23 2009-08-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
AU9296098A (en) * 1997-08-29 1999-03-16 Sharon N. Farrens In situ plasma wafer bonding method
JP4265882B2 (ja) * 2001-12-13 2009-05-20 忠弘 大見 相補型ｍｉｓ装置
JP4294935B2 (ja) * 2002-10-17 2009-07-15 株式会社ルネサステクノロジ 半導体装置
US6794718B2 (en) * 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
US7482214B2 (en) * 2003-12-30 2009-01-27 Texas Instruments Incorporated Transistor design and layout for performance improvement with strain
US7291886B2 (en) * 2004-06-21 2007-11-06 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
US7238589B2 (en) * 2004-11-01 2007-07-03 International Business Machines Corporation In-place bonding of microstructures
US7205639B2 (en) * 2005-03-09 2007-04-17 Infineon Technologies Ag Semiconductor devices with rotated substrates and methods of manufacture thereof
US7547637B2 (en) * 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
KR100655437B1 (ko) * 2005-08-09 2006-12-08 삼성전자주식회사 반도체 웨이퍼 및 그 제조방법
US20070145367A1 (en) * 2005-12-27 2007-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structure
FR2896620B1 (fr) * 2006-01-23 2008-05-30 Commissariat Energie Atomique Circuit integre tridimensionnel de type c-mos et procede de fabrication
DE102006019835B4 (de) * 2006-04-28 2011-05-12 Advanced Micro Devices, Inc., Sunnyvale Transistor mit einem Kanal mit Zugverformung, der entlang einer kristallographischen Orientierung mit erhöhter Ladungsträgerbeweglichkeit orientiert ist
US20070257322A1 (en) * 2006-05-08 2007-11-08 Freescale Semiconductor, Inc. Hybrid Transistor Structure and a Method for Making the Same
US7435639B2 (en) * 2006-05-31 2008-10-14 Freescale Semiconductor, Inc. Dual surface SOI by lateral epitaxial overgrowth
US7803670B2 (en) * 2006-07-20 2010-09-28 Freescale Semiconductor, Inc. Twisted dual-substrate orientation (DSO) substrates
DE102006046363B4 (de) * 2006-09-29 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Verringern von Kristalldefekten in Transistoren mit wieder aufgewachsenen flachen Übergängen durch geeignetes Auswählen von Kristallorientierungen
FR2915318B1 (fr) * 2007-04-20 2009-07-17 St Microelectronics Crolles 2 Procede de realisation d'un circuit electronique integre a deux portions de couches actives ayant des orientations cristallines differentes
US7759179B2 (en) * 2008-01-31 2010-07-20 International Business Machines Corporation Multi-gated, high-mobility, density improved devices
US8241970B2 (en) * 2008-08-25 2012-08-14 International Business Machines Corporation CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins
FR2935539B1 (fr) * 2008-08-26 2010-12-10 Commissariat Energie Atomique Circuit cmos tridimensionnel sur deux substrats desalignes et procede de realisation
US8368125B2 (en) * 2009-07-20 2013-02-05 International Business Machines Corporation Multiple orientation nanowires with gate stack stressors

Also Published As

Publication number Publication date
WO2010022856A1 (fr) 2010-03-04
US8569801B2 (en) 2013-10-29
FR2935539A1 (fr) 2010-03-05
US20110140178A1 (en) 2011-06-16
EP2319080A1 (fr) 2011-05-11

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