FR2999746B1 - Procede de generation d'une topographie d'un circuit integre fdsoi - Google Patents

Procede de generation d'une topographie d'un circuit integre fdsoi Download PDF

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Publication number
FR2999746B1
FR2999746B1 FR1261980A FR1261980A FR2999746B1 FR 2999746 B1 FR2999746 B1 FR 2999746B1 FR 1261980 A FR1261980 A FR 1261980A FR 1261980 A FR1261980 A FR 1261980A FR 2999746 B1 FR2999746 B1 FR 2999746B1
Authority
FR
France
Prior art keywords
fdsoi
integrated circuit
topography
generating
generating topography
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1261980A
Other languages
English (en)
Other versions
FR2999746A1 (fr
Inventor
Bastien Giraud
Philippe Flatresse
Matthieu Le Boulaire
Jean-Philippe Noel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
STMicroelectronics SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, STMicroelectronics SA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1261980A priority Critical patent/FR2999746B1/fr
Priority to US14/105,382 priority patent/US9092590B2/en
Publication of FR2999746A1 publication Critical patent/FR2999746A1/fr
Application granted granted Critical
Publication of FR2999746B1 publication Critical patent/FR2999746B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Architecture (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
FR1261980A 2012-12-13 2012-12-13 Procede de generation d'une topographie d'un circuit integre fdsoi Expired - Fee Related FR2999746B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1261980A FR2999746B1 (fr) 2012-12-13 2012-12-13 Procede de generation d'une topographie d'un circuit integre fdsoi
US14/105,382 US9092590B2 (en) 2012-12-13 2013-12-13 Method for generating a topography of an FDSOI integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1261980A FR2999746B1 (fr) 2012-12-13 2012-12-13 Procede de generation d'une topographie d'un circuit integre fdsoi
FR1261980 2012-12-13

Publications (2)

Publication Number Publication Date
FR2999746A1 FR2999746A1 (fr) 2014-06-20
FR2999746B1 true FR2999746B1 (fr) 2018-04-27

Family

ID=48170592

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1261980A Expired - Fee Related FR2999746B1 (fr) 2012-12-13 2012-12-13 Procede de generation d'une topographie d'un circuit integre fdsoi

Country Status (2)

Country Link
US (1) US9092590B2 (fr)
FR (1) FR2999746B1 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015021209A1 (fr) * 2013-08-06 2015-02-12 Ess Technology, Inc. Placement limité d'éléments connectés
JP2015122398A (ja) * 2013-12-24 2015-07-02 セイコーエプソン株式会社 半導体集積回路装置及びそのレイアウト設計方法
WO2016079918A1 (fr) * 2014-11-19 2016-05-26 株式会社ソシオネクスト Structure topologique de circuit intégré à semi-conducteur
US9607123B2 (en) * 2015-01-16 2017-03-28 United Microelectronics Corp. Method for performing deep n-typed well-correlated (DNW-correlated) antenna rule check of integrated circuit and semiconductor structure complying with DNW-correlated antenna rule
US9490245B1 (en) 2015-06-19 2016-11-08 Qualcomm Incorporated Circuit and layout for a high density antenna protection diode
US10068918B2 (en) 2015-09-21 2018-09-04 Globalfoundries Inc. Contacting SOI subsrates
US10269783B2 (en) * 2016-01-22 2019-04-23 Arm Limited Implant structure for area reduction
US10114919B2 (en) * 2016-02-12 2018-10-30 Globalfoundries Inc. Placing and routing method for implementing back bias in FDSOI
US9923527B2 (en) * 2016-05-06 2018-03-20 Globalfoundries Inc. Method, apparatus and system for back gate biasing for FD-SOI devices
US10002800B2 (en) 2016-05-13 2018-06-19 International Business Machines Corporation Prevention of charging damage in full-depletion devices
US10572620B2 (en) * 2017-08-02 2020-02-25 Oracle International Corporation Custom piecewise digital layout generation
US11749671B2 (en) * 2020-10-09 2023-09-05 Globalfoundries U.S. Inc. Integrated circuit structures with well boundary distal to substrate midpoint and methods to form the same
EP4304313A1 (fr) * 2022-07-06 2024-01-10 STMicroelectronics Crolles 2 SAS Dispositif semiconducteur du type silicium sur isolant comprenant un circuit de mémoire vive statique, et procédé de fabrication correspondant

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8293615B2 (en) * 2011-03-24 2012-10-23 International Business Machines Corporation Self-aligned dual depth isolation and method of fabrication
FR2975803B1 (fr) * 2011-05-24 2014-01-10 Commissariat Energie Atomique Circuit integre realise en soi comprenant des cellules adjacentes de differents types
US9040929B2 (en) * 2012-07-30 2015-05-26 International Business Machines Corporation Charge sensors using inverted lateral bipolar junction transistors

Also Published As

Publication number Publication date
FR2999746A1 (fr) 2014-06-20
US9092590B2 (en) 2015-07-28
US20140173544A1 (en) 2014-06-19

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