FR3017746B1 - Cellule memoire verticale ayant un implant drain-source flottant non auto-aligne - Google Patents

Cellule memoire verticale ayant un implant drain-source flottant non auto-aligne

Info

Publication number
FR3017746B1
FR3017746B1 FR1451297A FR1451297A FR3017746B1 FR 3017746 B1 FR3017746 B1 FR 3017746B1 FR 1451297 A FR1451297 A FR 1451297A FR 1451297 A FR1451297 A FR 1451297A FR 3017746 B1 FR3017746 B1 FR 3017746B1
Authority
FR
France
Prior art keywords
self
memory cell
vertical memory
source implant
floating drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1451297A
Other languages
English (en)
Other versions
FR3017746A1 (fr
Inventor
Marc Mantelli
Stephan Niel
Arnaud Regnier
Rosa Francesco La
Julien Delalleau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics International NV Switzerland
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1451297A priority Critical patent/FR3017746B1/fr
Priority to US14/625,356 priority patent/US9543311B2/en
Publication of FR3017746A1 publication Critical patent/FR3017746A1/fr
Application granted granted Critical
Publication of FR3017746B1 publication Critical patent/FR3017746B1/fr
Priority to US15/365,768 priority patent/US9876122B2/en
Priority to US15/852,826 priority patent/US10192999B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6894—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having one gate at least partly in a trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
FR1451297A 2014-02-18 2014-02-18 Cellule memoire verticale ayant un implant drain-source flottant non auto-aligne Active FR3017746B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1451297A FR3017746B1 (fr) 2014-02-18 2014-02-18 Cellule memoire verticale ayant un implant drain-source flottant non auto-aligne
US14/625,356 US9543311B2 (en) 2014-02-18 2015-02-18 Vertical memory cell with non-self-aligned floating drain-source implant
US15/365,768 US9876122B2 (en) 2014-02-18 2016-11-30 Vertical memory cell with non-self-aligned floating drain-source implant
US15/852,826 US10192999B2 (en) 2014-02-18 2017-12-22 Vertical memory cell with non-self-aligned floating drain-source implant

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1451297A FR3017746B1 (fr) 2014-02-18 2014-02-18 Cellule memoire verticale ayant un implant drain-source flottant non auto-aligne

Publications (2)

Publication Number Publication Date
FR3017746A1 FR3017746A1 (fr) 2015-08-21
FR3017746B1 true FR3017746B1 (fr) 2016-05-27

Family

ID=51168015

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1451297A Active FR3017746B1 (fr) 2014-02-18 2014-02-18 Cellule memoire verticale ayant un implant drain-source flottant non auto-aligne

Country Status (2)

Country Link
US (3) US9543311B2 (fr)
FR (1) FR3017746B1 (fr)

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* Cited by examiner, † Cited by third party
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FR3012672B1 (fr) * 2013-10-31 2017-04-14 Stmicroelectronics Rousset Cellule memoire comprenant des grilles de controle horizontale et verticale non auto-alignees
FR3017746B1 (fr) 2014-02-18 2016-05-27 Stmicroelectronics Rousset Cellule memoire verticale ayant un implant drain-source flottant non auto-aligne
US9917165B2 (en) * 2015-05-15 2018-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Memory cell structure for improving erase speed
FR3057393A1 (fr) 2016-10-11 2018-04-13 Stmicroelectronics (Rousset) Sas Circuit integre avec condensateur de decouplage dans une structure de type triple caisson
CN108806751B (zh) * 2017-04-26 2021-04-09 中芯国际集成电路制造(上海)有限公司 多次可程式闪存单元阵列及其操作方法、存储器件
FR3070535A1 (fr) 2017-08-28 2019-03-01 Stmicroelectronics (Crolles 2) Sas Circuit integre avec element capacitif a structure verticale, et son procede de fabrication
FR3070534A1 (fr) 2017-08-28 2019-03-01 Stmicroelectronics (Rousset) Sas Procede de fabrication d'elements capacitifs dans des tranchees
US10553708B2 (en) * 2017-08-29 2020-02-04 International Business Machines Corporation Twin gate tunnel field-effect transistor (FET)
FR3076660B1 (fr) 2018-01-09 2020-02-07 Stmicroelectronics (Rousset) Sas Dispositif integre de cellule capacitive de remplissage et procede de fabrication correspondant
US11621222B2 (en) 2018-01-09 2023-04-04 Stmicroelectronics (Rousset) Sas Integrated filler capacitor cell device and corresponding manufacturing method
US10482975B2 (en) * 2018-03-16 2019-11-19 Microchip Technology Incorporated Flash memory cell with dual erase modes for increased cell endurance
FR3080949B1 (fr) * 2018-05-04 2021-05-28 St Microelectronics Rousset Dispositif de memoire non volatile du type a piegeage de charges et procede de fabrication
FR3087027A1 (fr) 2018-10-08 2020-04-10 Stmicroelectronics (Rousset) Sas Element capacitif de puce electronique
US10762966B2 (en) * 2018-10-30 2020-09-01 Globalfoundries Singapore Pte. Ltd. Memory arrays and methods of forming the same
US11004785B2 (en) 2019-08-21 2021-05-11 Stmicroelectronics (Rousset) Sas Co-integrated vertically structured capacitive element and fabrication process
CN119317108B (zh) * 2023-07-13 2025-10-28 中芯国际集成电路制造(北京)有限公司 存储结构及其形成方法、存储器电路及其工作方法

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FR3012672B1 (fr) 2013-10-31 2017-04-14 Stmicroelectronics Rousset Cellule memoire comprenant des grilles de controle horizontale et verticale non auto-alignees
FR3012673B1 (fr) 2013-10-31 2017-04-14 St Microelectronics Rousset Memoire programmable par injection de porteurs chauds et procede de programmation d'une telle memoire
FR3017746B1 (fr) 2014-02-18 2016-05-27 Stmicroelectronics Rousset Cellule memoire verticale ayant un implant drain-source flottant non auto-aligne

Also Published As

Publication number Publication date
US10192999B2 (en) 2019-01-29
US20180145183A1 (en) 2018-05-24
US20170084749A1 (en) 2017-03-23
FR3017746A1 (fr) 2015-08-21
US9876122B2 (en) 2018-01-23
US20150236031A1 (en) 2015-08-20
US9543311B2 (en) 2017-01-10

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