FR3046878A1 - Procede de fabrication d'une interconnexion comprenant un via s'etendant au travers d'un substrat - Google Patents
Procede de fabrication d'une interconnexion comprenant un via s'etendant au travers d'un substrat Download PDFInfo
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- FR3046878A1 FR3046878A1 FR1650408A FR1650408A FR3046878A1 FR 3046878 A1 FR3046878 A1 FR 3046878A1 FR 1650408 A FR1650408 A FR 1650408A FR 1650408 A FR1650408 A FR 1650408A FR 3046878 A1 FR3046878 A1 FR 3046878A1
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- chamber
- copper
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- deposition
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/4401—Means for minimising impurities, e.g. dust, moisture or residual gas, in the reaction chamber
- C23C16/4405—Cleaning of reactor or parts inside the reactor by using reactive gases
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01332—Making the insulator
- H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
- H10D64/01344—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a nitrogen-containing ambient, e.g. N2O oxidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
- H10P14/3416—Nitrides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
- H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
- H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P70/00—Cleaning of wafers, substrates or parts of devices
- H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H10P70/12—Cleaning before device manufacture, i.e. Begin-Of-Line process by dry cleaning only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0402—Apparatus for fluid treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
- H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
- H10W20/039—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures also covering sidewalls of the conductive structures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/046—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being associated with interconnections of capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/425—Barrier, adhesion or liner layers
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Organic Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- General Chemical & Material Sciences (AREA)
- Mechanical Engineering (AREA)
- Electrochemistry (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemical Vapour Deposition (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
Abstract
Description
Claims (13)
- REVENDICATIONS1. Procédé de fabrication d’une interconnexion comprenant un via (V) s’étendant au travers d’un substrat (1), comprenant successivement : (a) le dépôt d’une couche (11) de nitrure de titane ou de nitrure de tantale sur une surface principale (1A) du substrat et sur la surface intérieure (10A, 10B) d’au moins un trou (10) s’étendant dans au moins une partie de l’épaisseur dudit substrat, (b) le dépôt d’une couche (12) de cuivre sur ladite couche (11) de nitrure de titane ou de nitrure de tantale, (c) le remplissage du trou (10) par du cuivre, ledit procédé étant caractérisé en ce que pendant l’étape (a) le substrat (1) est agencé dans une première chambre de dépôt (100) et en ce que ladite étape (a) comprend l’injection d’un précurseur de titane ou de tantale en phase gazeuse dans la chambre de dépôt par une première voie d’injection selon une première séquence d’impulsions et l’injection d’un gaz réactif à base d’azote dans la chambre de dépôt par une seconde voie d’injection distincte de la première voie d’injection selon une seconde séquence d’impulsions, la première séquence d’impulsions et la seconde séquence d’impulsions étant déphasées.
- 2. Procédé selon la revendication 1, caractérisé en ce que l’étape (c) de remplissage du trou (10) est mise en œuvre par électrodéposition de cuivre.
- 3. Procédé selon la revendication 1, caractérisé en ce que le remplissage du trou (10) est réalisé en poursuivant le dépôt de cuivre réalisé à l’étape (b).
- 4. Procédé selon l’une des revendications 1 à 3, caractérisé en ce que l’épaisseur de la couche (11) de nitrure de titane ou de nitrure de tantale déposée à l’étape (a) est inférieure ou égale à 100 nm.
- 5. Procédé selon l’une des revendications 1 à 4, caractérisé en ce que l’épaisseur de la couche (12) de cuivre déposée à l’étape (b) est comprise entre 50 et 300 nm.
- 6. Procédé selon l’une des revendications 1 à 5, caractérisé en ce que le dépôt de la couche (12) de cuivre à l’étape (b) est réalisé dans une seconde chambre de dépôt (200) différente de la première chambre (100).
- 7. Procédé selon la revendication 6, caractérisé en ce que l’étape (b) est mise en œuvre par dépôt chimique en phase vapeur.
- 8. Procédé selon l’une des revendications 6 ou 7, caractérisé en ce que la première et la seconde chambre de dépôt (100, 200) sont connectées séparément de manière étanche à une chambre intermédiaire (300) et en ce qu’entre les étapes (a) et (b), le substrat est transféré de la première chambre (100) à la seconde chambre (200) par la chambre intermédiaire (300) sous vide d’air.
- 9. Procédé selon l’une des revendications 1 à 8, caractérisé en ce que le via (V) présente un facteur de forme supérieur ou égal à 5 : 1.
- 10. Procédé selon l’une des revendications 1 à 9, caractérisé en ce qu’il comprend, après le remplissage du trou (10), l’enlèvement d’au moins une partie (1B) de l’épaisseur du substrat (1) opposée à la surface principale (1A) sur laquelle la couche de nitrure de titane ou de nitrure de tantale et la couche de cuivre ont été déposées de sorte à exposer l’intérieur du via (V) de sorte à rendre ledit via traversant.
- 11. Procédé selon l’une des revendications 1 à 10, caractérisé en ce qu’après l’étape (a), il comprend un nettoyage de la chambre (100) dans laquelle la couche (10) de nitrure de titane ou de nitrure de tantale a été déposée pour éliminer ledit nitrure de titane ou nitrure de tantale déposé sur une paroi intérieure de ladite chambre, ledit nettoyage étant effectué avec un gaz réactif composé de fluor et activé par une source plasma.
- 12. Procédé selon l’une des revendications 1 à 11, caractérisé en ce qu’après l’étape (b), il comprend un nettoyage de la chambre (200) dans laquelle la couche (11) de cuivre a été déposée pour éliminer ledit cuivre déposé sur une paroi intérieure de ladite chambre, ledit nettoyage comprenant les étapes suivantes : (i) oxydation du cuivre ; (ii) injection, selon une séquence d’impulsions, d’espèces chimiques adaptées pour volatiliser ledit cuivre oxydé, ladite étape (ii) débutant après le début de l’étape (i).
- 13. Dispositif pour la mise en œuvre d’un procédé selon l’une des revendications 1 à 12, caractérisé en ce qu’il comprend : - une première chambre de dépôt (100) étanche connectée à une source d’un précurseur de titane ou de tantale par une première voie d’injection et à une source d’un gaz réactif à base d’azote par une seconde voie d’injection distincte de la première voie, - une seconde chambre de dépôt (200) étanche connectée à une source de cuivre et - une chambre intermédiaire (300) à laquelle sont connectées séparément de manière étanche la première et la seconde chambre de dépôt (100, 200).
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1650408A FR3046878B1 (fr) | 2016-01-19 | 2016-01-19 | Procede de fabrication d'une interconnexion comprenant un via s'etendant au travers d'un substrat |
| CN201780007371.4A CN108475660A (zh) | 2016-01-19 | 2017-01-16 | 用于制造包括贯穿基板延伸的导电孔的互连部的方法 |
| PCT/EP2017/050761 WO2017125336A1 (fr) | 2016-01-19 | 2017-01-16 | Procede de fabrication d'une interconnexion comprenant un via s' etendant au travers d'un substrat |
| KR1020187023627A KR20180118627A (ko) | 2016-01-19 | 2017-01-16 | 기판을 통해 연장된 비아를 포함하는 인터커넥션을 제조하는 방법 |
| TW106101376A TW201733066A (zh) | 2016-01-19 | 2017-01-16 | 製造包含穿過基板延伸之通孔之互連的方法 |
| US16/070,506 US11114340B2 (en) | 2016-01-19 | 2017-01-16 | Method for producing an interconnection comprising a via extending through a substrate |
| EP17701653.2A EP3405974A1 (fr) | 2016-01-19 | 2017-01-16 | Procede de fabrication d'une interconnexion comprenant un via s' etendant au travers d'un substrat |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1650408 | 2016-01-19 | ||
| FR1650408A FR3046878B1 (fr) | 2016-01-19 | 2016-01-19 | Procede de fabrication d'une interconnexion comprenant un via s'etendant au travers d'un substrat |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR3046878A1 true FR3046878A1 (fr) | 2017-07-21 |
| FR3046878B1 FR3046878B1 (fr) | 2018-05-18 |
Family
ID=55590042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR1650408A Active FR3046878B1 (fr) | 2016-01-19 | 2016-01-19 | Procede de fabrication d'une interconnexion comprenant un via s'etendant au travers d'un substrat |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US11114340B2 (fr) |
| EP (1) | EP3405974A1 (fr) |
| KR (1) | KR20180118627A (fr) |
| CN (1) | CN108475660A (fr) |
| FR (1) | FR3046878B1 (fr) |
| TW (1) | TW201733066A (fr) |
| WO (1) | WO2017125336A1 (fr) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102619482B1 (ko) * | 2019-10-25 | 2024-01-02 | 에이에스엠 아이피 홀딩 비.브이. | 막 증착 공정에서의 정상 펄스 프로파일의 변형 |
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| US20010034123A1 (en) * | 2000-04-20 | 2001-10-25 | In-Sang Jeon | Method of manufacturing a barrier metal layer using atomic layer deposition |
| WO2003008663A1 (fr) * | 2001-07-16 | 2003-01-30 | Applied Materials, Inc. | Formation de films de nitrure de titane au moyen d'un processus de depot cyclique |
| US20060019495A1 (en) * | 2004-07-20 | 2006-01-26 | Applied Materials, Inc. | Atomic layer deposition of tantalum-containing materials using the tantalum precursor taimata |
| US20080242078A1 (en) * | 2007-03-30 | 2008-10-02 | Asm Nutool, Inc. | Process of filling deep vias for 3-d integration of substrates |
| WO2009042713A1 (fr) * | 2007-09-28 | 2009-04-02 | Applied Materials, Inc. | Dépôt en phase vapeur de matériaux à base de tungstène |
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|---|---|---|---|---|
| US5186718A (en) * | 1989-05-19 | 1993-02-16 | Applied Materials, Inc. | Staged-vacuum wafer processing system and method |
| US6284052B2 (en) * | 1998-08-19 | 2001-09-04 | Sharp Laboratories Of America, Inc. | In-situ method of cleaning a metal-organic chemical vapor deposition chamber |
| US8696875B2 (en) * | 1999-10-08 | 2014-04-15 | Applied Materials, Inc. | Self-ionized and inductively-coupled plasma for sputtering and resputtering |
| US6916398B2 (en) * | 2001-10-26 | 2005-07-12 | Applied Materials, Inc. | Gas delivery apparatus and method for atomic layer deposition |
| US6784096B2 (en) * | 2002-09-11 | 2004-08-31 | Applied Materials, Inc. | Methods and apparatus for forming barrier layers in high aspect ratio vias |
| KR100667561B1 (ko) * | 2005-02-18 | 2007-01-11 | 주식회사 아이피에스 | 박막 증착 방법 |
| US20100206737A1 (en) * | 2009-02-17 | 2010-08-19 | Preisser Robert F | Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv) |
| US8531033B2 (en) * | 2009-09-07 | 2013-09-10 | Advanced Interconnect Materials, Llc | Contact plug structure, semiconductor device, and method for forming contact plug |
| US8907457B2 (en) * | 2010-02-08 | 2014-12-09 | Micron Technology, Inc. | Microelectronic devices with through-substrate interconnects and associated methods of manufacturing |
| KR20120031811A (ko) * | 2010-09-27 | 2012-04-04 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| FR3018825B1 (fr) | 2014-03-21 | 2017-09-01 | Altatech Semiconductor | Procede de depot en phase gazeuse |
-
2016
- 2016-01-19 FR FR1650408A patent/FR3046878B1/fr active Active
-
2017
- 2017-01-16 WO PCT/EP2017/050761 patent/WO2017125336A1/fr not_active Ceased
- 2017-01-16 US US16/070,506 patent/US11114340B2/en active Active
- 2017-01-16 KR KR1020187023627A patent/KR20180118627A/ko not_active Ceased
- 2017-01-16 CN CN201780007371.4A patent/CN108475660A/zh active Pending
- 2017-01-16 EP EP17701653.2A patent/EP3405974A1/fr not_active Withdrawn
- 2017-01-16 TW TW106101376A patent/TW201733066A/zh unknown
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010034123A1 (en) * | 2000-04-20 | 2001-10-25 | In-Sang Jeon | Method of manufacturing a barrier metal layer using atomic layer deposition |
| WO2003008663A1 (fr) * | 2001-07-16 | 2003-01-30 | Applied Materials, Inc. | Formation de films de nitrure de titane au moyen d'un processus de depot cyclique |
| US20060019495A1 (en) * | 2004-07-20 | 2006-01-26 | Applied Materials, Inc. | Atomic layer deposition of tantalum-containing materials using the tantalum precursor taimata |
| US20080242078A1 (en) * | 2007-03-30 | 2008-10-02 | Asm Nutool, Inc. | Process of filling deep vias for 3-d integration of substrates |
| WO2009042713A1 (fr) * | 2007-09-28 | 2009-04-02 | Applied Materials, Inc. | Dépôt en phase vapeur de matériaux à base de tungstène |
Also Published As
| Publication number | Publication date |
|---|---|
| FR3046878B1 (fr) | 2018-05-18 |
| CN108475660A (zh) | 2018-08-31 |
| KR20180118627A (ko) | 2018-10-31 |
| WO2017125336A1 (fr) | 2017-07-27 |
| US20210202314A1 (en) | 2021-07-01 |
| US11114340B2 (en) | 2021-09-07 |
| TW201733066A (zh) | 2017-09-16 |
| EP3405974A1 (fr) | 2018-11-28 |
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