FR3058567B1 - Circuit integre comportant une structure antifusible, et procede de realisation - Google Patents

Circuit integre comportant une structure antifusible, et procede de realisation Download PDF

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Publication number
FR3058567B1
FR3058567B1 FR1660777A FR1660777A FR3058567B1 FR 3058567 B1 FR3058567 B1 FR 3058567B1 FR 1660777 A FR1660777 A FR 1660777A FR 1660777 A FR1660777 A FR 1660777A FR 3058567 B1 FR3058567 B1 FR 3058567B1
Authority
FR
France
Prior art keywords
integrated circuit
antifouble
making same
antifusible
br1b
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1660777A
Other languages
English (en)
Other versions
FR3058567A1 (fr
Inventor
Pascal FORNARA
Christian Rivero
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1660777A priority Critical patent/FR3058567B1/fr
Priority to CN201720453604.0U priority patent/CN207217500U/zh
Priority to CN201710282882.9A priority patent/CN108063131B/zh
Priority to US15/610,323 priority patent/US10242944B2/en
Publication of FR3058567A1 publication Critical patent/FR3058567A1/fr
Application granted granted Critical
Publication of FR3058567B1 publication Critical patent/FR3058567B1/fr
Priority to US16/270,356 priority patent/US10685912B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/80—Arrangements for protection of devices protecting against overcurrent or overload, e.g. fuses or shunts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/491—Antifuses, i.e. interconnections changeable from non-conductive to conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Le circuit intégré comprend, au dessus d'un substrat, une partie d'interconnexion, comportant plusieurs niveaux de métallisation séparés par une région isolante (RIS). Le circuit intégré comprend en outre au sein de ladite partie d'interconnexion,, au moins une structure antifusible (STR), enrobée dans une partie de ladite région isolante (RIS), la structure antifusible comportant une poutre (PTR) maintenue en deux endroits différents par deux bras (BR1A, BR1B), un corps (BTA) et une zone isolante antifusible (ZSF), la poutre (PTR), le corps (BTA) et les bras (BR1A, BR1B) étant métalliques et situés au sein d'un même niveau de métallisation, ledit corps et ladite poutre étant mutuellement en contact par l'intermédiaire de ladite zone isolante antifusible (ZSF) configurée pour être claquée en présence d'une différence de potentiel de claquage entre ledit corps et ladite poutre.
FR1660777A 2016-11-08 2016-11-08 Circuit integre comportant une structure antifusible, et procede de realisation Active FR3058567B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR1660777A FR3058567B1 (fr) 2016-11-08 2016-11-08 Circuit integre comportant une structure antifusible, et procede de realisation
CN201720453604.0U CN207217500U (zh) 2016-11-08 2017-04-26 集成电路和集成电路系统
CN201710282882.9A CN108063131B (zh) 2016-11-08 2017-04-26 包括反熔丝结构的集成电路及其制造方法
US15/610,323 US10242944B2 (en) 2016-11-08 2017-05-31 Integrated circuit comprising an antifuse structure and method of realizing
US16/270,356 US10685912B2 (en) 2016-11-08 2019-02-07 Integrated circuit comprising an antifuse structure and method of realizing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1660777 2016-11-08
FR1660777A FR3058567B1 (fr) 2016-11-08 2016-11-08 Circuit integre comportant une structure antifusible, et procede de realisation

Publications (2)

Publication Number Publication Date
FR3058567A1 FR3058567A1 (fr) 2018-05-11
FR3058567B1 true FR3058567B1 (fr) 2019-01-25

Family

ID=58213205

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1660777A Active FR3058567B1 (fr) 2016-11-08 2016-11-08 Circuit integre comportant une structure antifusible, et procede de realisation

Country Status (3)

Country Link
US (2) US10242944B2 (fr)
CN (2) CN207217500U (fr)
FR (1) FR3058567B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3058567B1 (fr) * 2016-11-08 2019-01-25 Stmicroelectronics (Rousset) Sas Circuit integre comportant une structure antifusible, et procede de realisation
US11296101B2 (en) 2020-03-27 2022-04-05 Sandisk Technologies Llc Three-dimensional memory device including an inter-tier etch stop layer and method of making the same
US12160989B2 (en) 2022-04-08 2024-12-03 Sandisk Technologies Llc Three-dimensional memory device including an isolation-trench etch stop layer and methods for forming the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3421574B2 (ja) * 1998-05-21 2003-06-30 株式会社東芝 半導体装置
JP3466929B2 (ja) * 1998-10-05 2003-11-17 株式会社東芝 半導体装置
US6515343B1 (en) * 1998-11-19 2003-02-04 Quicklogic Corporation Metal-to-metal antifuse with non-conductive diffusion barrier
US20030080839A1 (en) * 2001-10-31 2003-05-01 Wong Marvin Glenn Method for improving the power handling capacity of MEMS switches
JP4489651B2 (ja) * 2005-07-22 2010-06-23 株式会社日立製作所 半導体装置およびその製造方法
JP4191202B2 (ja) * 2006-04-26 2008-12-03 エルピーダメモリ株式会社 不揮発性記憶素子を搭載した半導体記憶装置
FR2935061A1 (fr) * 2008-08-13 2010-02-19 St Microelectronics Rousset Dispositif de detection d'une attaque d'un circuit integre
FR2984009B1 (fr) * 2011-12-09 2014-01-03 St Microelectronics Rousset Dispositif mecanique de commutation electrique integre
US9502424B2 (en) * 2012-06-29 2016-11-22 Qualcomm Incorporated Integrated circuit device featuring an antifuse and method of making same
CN106030793B (zh) * 2014-03-24 2018-10-26 英特尔公司 使用间隔体击穿的反熔丝元件
CN105826297B (zh) * 2015-01-06 2018-08-10 中芯国际集成电路制造(上海)有限公司 反熔丝及其形成方法
FR3058567B1 (fr) * 2016-11-08 2019-01-25 Stmicroelectronics (Rousset) Sas Circuit integre comportant une structure antifusible, et procede de realisation

Also Published As

Publication number Publication date
US10242944B2 (en) 2019-03-26
US20180130740A1 (en) 2018-05-10
CN108063131B (zh) 2021-03-30
CN207217500U (zh) 2018-04-10
US20190172785A1 (en) 2019-06-06
US10685912B2 (en) 2020-06-16
FR3058567A1 (fr) 2018-05-11
CN108063131A (zh) 2018-05-22

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