FR3100349B1 - Communication sur bus I2C - Google Patents

Communication sur bus I2C Download PDF

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Publication number
FR3100349B1
FR3100349B1 FR1909470A FR1909470A FR3100349B1 FR 3100349 B1 FR3100349 B1 FR 3100349B1 FR 1909470 A FR1909470 A FR 1909470A FR 1909470 A FR1909470 A FR 1909470A FR 3100349 B1 FR3100349 B1 FR 3100349B1
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FR
France
Prior art keywords
bus
communication
receiver device
recorded
rising edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1909470A
Other languages
English (en)
Other versions
FR3100349A1 (fr
Inventor
Yves Magnaud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grand Ouest SAS
Original Assignee
STMicroelectronics Grand Ouest SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Grand Ouest SAS filed Critical STMicroelectronics Grand Ouest SAS
Priority to FR1909470A priority Critical patent/FR3100349B1/fr
Priority to US17/003,764 priority patent/US11580052B2/en
Priority to CN202010883545.7A priority patent/CN112445744B/zh
Publication of FR3100349A1 publication Critical patent/FR3100349A1/fr
Application granted granted Critical
Publication of FR3100349B1 publication Critical patent/FR3100349B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4825—Interrupt from clock, e.g. time of day
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Information Transfer Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Small-Scale Networks (AREA)

Abstract

Communication sur bus I2C La présente description concerne un procédé de communication par bus I2C (6) entre un dispositif émetteur (4) et un dispositif récepteur (5), dans lequel : - un front montant d'un signal d'horloge (SCL) du bus I2C (6), suivant directement une condition de démarrage d'une communication I2C, est enregistré ; et - quand une interruption est générée au sein du dispositif récepteur (5), ledit dispositif récepteur vérifie si ledit front montant a été enregistré. Figure pour l'abrégé : Fig. 4
FR1909470A 2019-08-28 2019-08-28 Communication sur bus I2C Active FR3100349B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1909470A FR3100349B1 (fr) 2019-08-28 2019-08-28 Communication sur bus I2C
US17/003,764 US11580052B2 (en) 2019-08-28 2020-08-26 I2C communication
CN202010883545.7A CN112445744B (zh) 2019-08-28 2020-08-28 I2c通信

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1909470A FR3100349B1 (fr) 2019-08-28 2019-08-28 Communication sur bus I2C
FR1909470 2019-08-28

Publications (2)

Publication Number Publication Date
FR3100349A1 FR3100349A1 (fr) 2021-03-05
FR3100349B1 true FR3100349B1 (fr) 2022-07-08

Family

ID=68582003

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1909470A Active FR3100349B1 (fr) 2019-08-28 2019-08-28 Communication sur bus I2C

Country Status (3)

Country Link
US (1) US11580052B2 (fr)
CN (1) CN112445744B (fr)
FR (1) FR3100349B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114020679B (zh) * 2021-11-12 2023-11-07 中国船舶集团有限公司第七一一研究所 I2c总线控制电路及用于船舶的电路系统
CN119382836B (zh) * 2024-12-26 2025-03-11 北京经纬恒润科技股份有限公司 一种串行通信总线验证方法、装置、系统及存储介质

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7171461B2 (en) * 1996-07-23 2007-01-30 Server Technology, Inc. Network remote power management outlet strip
JP2008539645A (ja) * 2005-04-29 2008-11-13 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 状態マシンを用いたｉ２ｃスレーブ／マスタインタフェース機能強化
KR100684553B1 (ko) * 2006-01-12 2007-02-22 엠텍비젼 주식회사 듀얼 포트 메모리와 결합되는 마이크로 프로세서
CN100480923C (zh) * 2006-01-13 2009-04-22 深圳创维－Rgb电子有限公司 I2c总线从控制器软实现方法
DE102006004346A1 (de) * 2006-01-30 2007-10-18 Deutsche Thomson-Brandt Gmbh Datenbusschnittstelle mit abschaltbarem Takt
CN101399635A (zh) * 2008-09-28 2009-04-01 中兴通讯股份有限公司 通讯波特率自适应方法、装置以及主机
TWI397896B (zh) * 2009-01-14 2013-06-01 Novatek Microelectronics Corp 使用單一資料致能訊號來控制顯示器時序之方法及相關時序控制電路
CN101763331B (zh) * 2010-01-18 2014-04-09 中兴通讯股份有限公司 一种实现i2c总线控制的系统及方法
CN101969721B (zh) * 2010-09-16 2013-04-17 深圳市明微电子股份有限公司 双线数据传输的方法及装置
EP3048536B1 (fr) * 2011-10-05 2020-02-19 Analog Devices, Inc. Système de communication à deux fils pour la distribution de puissance et de données à grande vitesse
JP2016004388A (ja) * 2014-06-16 2016-01-12 富士通株式会社 通信システム及び電子回路
GB2537856A (en) * 2015-04-28 2016-11-02 Nordic Semiconductor Asa Communication between intergrated circuits
CN105426338A (zh) * 2015-10-30 2016-03-23 深圳市芯海科技有限公司 一种i2c唤醒mcu电路及唤醒方法
JP2019096960A (ja) * 2017-11-20 2019-06-20 富士通株式会社 伝送装置及び伝送方法

Also Published As

Publication number Publication date
US20210064567A1 (en) 2021-03-04
FR3100349A1 (fr) 2021-03-05
CN112445744A (zh) 2021-03-05
US11580052B2 (en) 2023-02-14
CN112445744B (zh) 2024-04-02

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