FR3119929B1 - Procede de fabrication d’une structure adaptee pour les applications radiofrequences, et substrat support pour ladite structure - Google Patents

Procede de fabrication d’une structure adaptee pour les applications radiofrequences, et substrat support pour ladite structure Download PDF

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Publication number
FR3119929B1
FR3119929B1 FR2101411A FR2101411A FR3119929B1 FR 3119929 B1 FR3119929 B1 FR 3119929B1 FR 2101411 A FR2101411 A FR 2101411A FR 2101411 A FR2101411 A FR 2101411A FR 3119929 B1 FR3119929 B1 FR 3119929B1
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France
Prior art keywords
support substrate
ohm
temperature
interstitial oxygen
defects
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Active
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FR2101411A
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English (en)
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FR3119929A1 (fr
Inventor
Romain Bouveyron
Isabelle Bertrand
Maël Coche
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Soitec SA
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Soitec SA
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Publication date
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Priority to FR2101411A priority Critical patent/FR3119929B1/fr
Publication of FR3119929A1 publication Critical patent/FR3119929A1/fr
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Publication of FR3119929B1 publication Critical patent/FR3119929B1/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/20—Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

L’invention concerne un procédé de fabrication d’une structure adaptée pour des applications radiofréquences, comprenant les étapes suivantes : a) la fourniture d’un substrat initial en silicium monocristallin, présentant une teneur en oxygène interstitiel comprise entre 6.50x1017 Oi/cm3 et 11.52x1017 Oi/cm3, et une résistivité comprise entre 200 ohm.cm et 1500 ohm.cm, le substrat initial étant destiné à former un substrat support après avoir subi successivement les étapes b) et c) subséquentes, b) l’application d’un premier traitement thermique comprenant un plateau à une température comprise entre 1100°C et 1300°C, et une rampe de descente en température supérieure ou égale à 40°C/s, sous atmosphère neutre, pour injecter des défauts de type lacunes dans le substrat initial destinés à former des centres de nucléation favorables à une précipitation de l’oxygène interstitiel, c) l’application d’un deuxième traitement thermique comprenant une première séquence de recuit à une température comprise entre 600°C et 900°C, et une deuxième séquence de recuit à une température comprise entre 950°C et 1100°C, pour générer la précipitation de l’oxygène interstitiel sous forme de micro-défauts et former le substrat support pour la structure. L’invention concerne également un substrat support en silicium monocristallin, présentant une teneur en oxygène interstitiel (Oi) inférieure ou égale à 8,5x1017 Oi/cm3, une résistivité comprise entre 200 ohm.cm et 1500 ohm.cm, et une concentration en micro-défauts (BMD) comprise entre 1x109/cm3 et 3x1010/cm3. Pas de Figure
FR2101411A 2021-02-15 2021-02-15 Procede de fabrication d’une structure adaptee pour les applications radiofrequences, et substrat support pour ladite structure Active FR3119929B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR2101411A FR3119929B1 (fr) 2021-02-15 2021-02-15 Procede de fabrication d’une structure adaptee pour les applications radiofrequences, et substrat support pour ladite structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2101411 2021-02-15
FR2101411A FR3119929B1 (fr) 2021-02-15 2021-02-15 Procede de fabrication d’une structure adaptee pour les applications radiofrequences, et substrat support pour ladite structure

Publications (2)

Publication Number Publication Date
FR3119929A1 FR3119929A1 (fr) 2022-08-19
FR3119929B1 true FR3119929B1 (fr) 2023-11-03

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FR2101411A Active FR3119929B1 (fr) 2021-02-15 2021-02-15 Procede de fabrication d’une structure adaptee pour les applications radiofrequences, et substrat support pour ladite structure

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FR (1) FR3119929B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3155956B1 (fr) * 2023-11-24 2025-10-24 Soitec Silicon On Insulator Procédé de fabrication d’une structure SOI notamment adaptée pour les applications photoniques, et substrat support pour ladite structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1087041B1 (fr) * 1999-03-16 2009-01-07 Shin-Etsu Handotai Co., Ltd Procede de production d'une tranche de silicium et tranche de silicium ainsi obtenue
JP2002009081A (ja) * 2000-06-26 2002-01-11 Toshiba Corp 半導体装置及びその製造方法
FR2838865B1 (fr) * 2002-04-23 2005-10-14 Soitec Silicon On Insulator Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee
FR3051968B1 (fr) * 2016-05-25 2018-06-01 Soitec Procede de fabrication d'un substrat semi-conducteur a haute resistivite

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Publication number Publication date
FR3119929A1 (fr) 2022-08-19

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