FR3125897B1 - Procédé pour optimiser un fonctionnement d’un élément sécurisé - Google Patents

Procédé pour optimiser un fonctionnement d’un élément sécurisé Download PDF

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Publication number
FR3125897B1
FR3125897B1 FR2108329A FR2108329A FR3125897B1 FR 3125897 B1 FR3125897 B1 FR 3125897B1 FR 2108329 A FR2108329 A FR 2108329A FR 2108329 A FR2108329 A FR 2108329A FR 3125897 B1 FR3125897 B1 FR 3125897B1
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FR
France
Prior art keywords
secure element
list
memory
authorized
operations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2108329A
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English (en)
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FR3125897A1 (fr
Inventor
Giudice Lauren Marjorie Del
Hsin-I Huang (Amanda)
Eric Therene
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Idemia France SAS
Original Assignee
Idemia Identity and Security France SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Idemia Identity and Security France SAS filed Critical Idemia Identity and Security France SAS
Priority to FR2108329A priority Critical patent/FR3125897B1/fr
Publication of FR3125897A1 publication Critical patent/FR3125897A1/fr
Application granted granted Critical
Publication of FR3125897B1 publication Critical patent/FR3125897B1/fr
Active legal-status Critical Current
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1052—Security improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7211—Wear leveling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Read Only Memory (AREA)
  • Storage Device Security (AREA)

Abstract

La présente invention concerne un procédé pour optimiser un fonctionnement d’un élément sécurisé, l’élément sécurisé comprenant une mémoire, l’élément sécurisé étant configuré par une liste d’opérations autorisées, le procédé comprenant : a. recevoir une commande d’effacement ou d’écriture de données dans la mémoire ; et b. exécuter la commande reçue uniquement si la commande reçue correspond à une opération autorisée de la liste d’opérations autorisées. Le procédé comprend en outre : c. déterminer un indicateur d’un état d’usure globale de la mémoire ; et d. si l’indicateur déterminé indique que l’état d’usure globale de la mémoire est supérieur à un seuil prédéfini, réduire la liste d’opérations autorisées en retirant des opérations de ladite liste. [Fig. 4]
FR2108329A 2021-07-30 2021-07-30 Procédé pour optimiser un fonctionnement d’un élément sécurisé Active FR3125897B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR2108329A FR3125897B1 (fr) 2021-07-30 2021-07-30 Procédé pour optimiser un fonctionnement d’un élément sécurisé

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2108329A FR3125897B1 (fr) 2021-07-30 2021-07-30 Procédé pour optimiser un fonctionnement d’un élément sécurisé
FR2108329 2021-07-30

Publications (2)

Publication Number Publication Date
FR3125897A1 FR3125897A1 (fr) 2023-02-03
FR3125897B1 true FR3125897B1 (fr) 2025-01-17

Family

ID=78649378

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2108329A Active FR3125897B1 (fr) 2021-07-30 2021-07-30 Procédé pour optimiser un fonctionnement d’un élément sécurisé

Country Status (1)

Country Link
FR (1) FR3125897B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4593436A1 (fr) * 2024-01-29 2025-07-30 Giesecke+Devrient Mobile Security Germany GmbH Fourniture fiable de sim distant par euicc

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2977047B1 (fr) 2011-06-22 2013-08-16 Starchip Procede de gestion de l'endurance de memoires non volatiles.
CN108197503B (zh) * 2017-12-15 2020-09-15 杭州中天微系统有限公司 一种为间接访问存储控制器增加保护功能的装置
US10936213B2 (en) * 2019-03-13 2021-03-02 Micron Technology, Inc. Techniques for secure writes by non-privileged users
FR3104280B1 (fr) * 2019-12-06 2021-11-26 Thales Sa Systeme electronique securise comportant un processeur et un composant memoire ; composant programmable associe

Also Published As

Publication number Publication date
FR3125897A1 (fr) 2023-02-03

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