FR3133482B1 - Substrat d’interconnexion et procédé de fabrication d’un tel substrat - Google Patents

Substrat d’interconnexion et procédé de fabrication d’un tel substrat Download PDF

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Publication number
FR3133482B1
FR3133482B1 FR2202142A FR2202142A FR3133482B1 FR 3133482 B1 FR3133482 B1 FR 3133482B1 FR 2202142 A FR2202142 A FR 2202142A FR 2202142 A FR2202142 A FR 2202142A FR 3133482 B1 FR3133482 B1 FR 3133482B1
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FR
France
Prior art keywords
interconnection
substrate
metal
support
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2202142A
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English (en)
Other versions
FR3133482A1 (fr
Inventor
Fanny Laporte
Jerome Lopez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grenoble 2 SAS
Original Assignee
STMicroelectronics Grenoble 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Grenoble 2 SAS filed Critical STMicroelectronics Grenoble 2 SAS
Priority to FR2202142A priority Critical patent/FR3133482B1/fr
Priority to US18/118,513 priority patent/US20230290712A1/en
Publication of FR3133482A1 publication Critical patent/FR3133482A1/fr
Application granted granted Critical
Publication of FR3133482B1 publication Critical patent/FR3133482B1/fr
Priority to US19/305,228 priority patent/US20250372403A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/695—Organic materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Substrat d’interconnexion et procédé de fabrication d’un tel substrat La présente description concerne un substrat d’interconnexion (300) comprenant :- un support thermomécanique (310) traversé par au moins un trou d’interconnexion électrique (311) ;- un premier réseau d’interconnexion (330a) sur une première face (310a) du support; et- un deuxième réseau d’interconnexion (330b) sur une deuxième face (310b) du support;chaque réseau d’interconnexion comportant :- au moins un niveau d’interconnexion, chaque niveau d’interconnexion comprenant au moins une piste métallique (331a, 333a, 331b, 333b) à partir de laquelle s’étend au moins un via métallique (332a, 334a, 332b, 334b), la au moins une piste métallique et le au moins un via métallique étant noyés dans une couche d’isolant de sorte que le au moins un via affleure à la surface de ladite couche d’isolant la plus éloignée du support ; et- au moins une piste métallique (335a, 335b) en protrusion sur la couche d’isolant du dernier niveau d’interconnexion ;les vias métalliques étant adaptés à relier entre eux deux niveaux adjacents et/ou le dernier niveau avec la au moins une piste métallique en protrusion. Figure pour l'abrégé : Fig. 3
FR2202142A 2022-03-11 2022-03-11 Substrat d’interconnexion et procédé de fabrication d’un tel substrat Active FR3133482B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR2202142A FR3133482B1 (fr) 2022-03-11 2022-03-11 Substrat d’interconnexion et procédé de fabrication d’un tel substrat
US18/118,513 US20230290712A1 (en) 2022-03-11 2023-03-07 Interconnection substrate and method of manufacturing such a substrate
US19/305,228 US20250372403A1 (en) 2022-03-11 2025-08-20 Interconnection substrate and method of manufacturing such a substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2202142A FR3133482B1 (fr) 2022-03-11 2022-03-11 Substrat d’interconnexion et procédé de fabrication d’un tel substrat
FR2202142 2022-03-11

Publications (2)

Publication Number Publication Date
FR3133482A1 FR3133482A1 (fr) 2023-09-15
FR3133482B1 true FR3133482B1 (fr) 2025-02-28

Family

ID=82694062

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2202142A Active FR3133482B1 (fr) 2022-03-11 2022-03-11 Substrat d’interconnexion et procédé de fabrication d’un tel substrat

Country Status (2)

Country Link
US (1) US20230290712A1 (fr)
FR (1) FR3133482B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119626911B (zh) * 2024-11-28 2025-10-21 宏茂微电子(上海)有限公司 一种多层封装玻璃基板的制作方法及结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL128200A (en) * 1999-01-24 2003-11-23 Amitec Advanced Multilayer Int Chip carrier substrate
JP3778773B2 (ja) * 2000-05-09 2006-05-24 三洋電機株式会社 板状体および半導体装置の製造方法
KR100797716B1 (ko) * 2006-03-21 2008-01-23 삼성전기주식회사 회로기판이 없는 ｌｅｄ-백라이트유닛 및 그 제조방법
US7682972B2 (en) * 2006-06-01 2010-03-23 Amitec-Advanced Multilayer Interconnect Technoloiges Ltd. Advanced multilayer coreless support structures and method for their fabrication
JP5094323B2 (ja) * 2007-10-15 2012-12-12 新光電気工業株式会社 配線基板の製造方法
JP2018073890A (ja) * 2016-10-25 2018-05-10 イビデン株式会社 プリント配線板およびプリント配線板の製造方法
JP2019117911A (ja) * 2017-12-27 2019-07-18 イビデン株式会社 多層配線板
US10978417B2 (en) * 2019-04-29 2021-04-13 Advanced Semiconductor Engineering, Inc. Wiring structure and method for manufacturing the same
US11616026B2 (en) * 2020-01-17 2023-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture

Also Published As

Publication number Publication date
FR3133482A1 (fr) 2023-09-15
US20230290712A1 (en) 2023-09-14

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