FR3134907B1 - Procédé de surveillance d’une exécution d’une portion de code programme et système sur puce correspondant - Google Patents

Procédé de surveillance d’une exécution d’une portion de code programme et système sur puce correspondant

Info

Publication number
FR3134907B1
FR3134907B1 FR2203873A FR2203873A FR3134907B1 FR 3134907 B1 FR3134907 B1 FR 3134907B1 FR 2203873 A FR2203873 A FR 2203873A FR 2203873 A FR2203873 A FR 2203873A FR 3134907 B1 FR3134907 B1 FR 3134907B1
Authority
FR
France
Prior art keywords
rst
code portion
selected code
execution
monitoring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2203873A
Other languages
English (en)
Other versions
FR3134907A1 (fr
Inventor
Michel Jaouen
Loic Pallardy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grand Ouest SAS
Original Assignee
STMicroelectronics Grand Ouest SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Grand Ouest SAS filed Critical STMicroelectronics Grand Ouest SAS
Priority to FR2203873A priority Critical patent/FR3134907B1/fr
Priority to US18/306,032 priority patent/US12339762B2/en
Priority to CN202310460465.4A priority patent/CN116956269A/zh
Publication of FR3134907A1 publication Critical patent/FR3134907A1/fr
Application granted granted Critical
Publication of FR3134907B1 publication Critical patent/FR3134907B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Prevention of errors by analysis, debugging or testing of software
    • G06F11/3604Analysis of software for verifying properties of programs
    • G06F11/3612Analysis of software for verifying properties of programs by runtime analysis
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/52Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G06F21/575Secure boot

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

Le procédé de surveillance d’une exécution d’une portion de code programme sélectionnée (Rst) et enregistrée dans une plage d’adresses mémoires (AddRst) entre une adresse de début (s) et une adresse de fin (e), comprend : - un démarrage d’un chronométrage (CNT) lorsqu’un compteur programme (PC) pointe l’adresse de début de ladite portion de code sélectionnée (s{Rst}) ; - une comparaison (CMP) des valeurs courantes du compteur programme (PC) avec un jeu d’adresses cibles spécifiques à ladite portion de code sélectionnée (TRGT{Rst}) comportant l’adresse de fin de ladite portion de code sélectionnée (e{Rst}) ; - un arrêt du chronométrage (CNT) lorsque le compteur programme (PC) pointe l’adresse de fin de ladite portion de code sélectionnée (e{Rst}) ; - une génération d’un signal d’erreur (Err) si la durée du chronométrage est en dehors d’une gamme de durées nominale (NmnlRng) spécifique à ladite portion de code sélectionnée (Rst). Figure pour l’abrégé : Fig 1
FR2203873A 2022-04-26 2022-04-26 Procédé de surveillance d’une exécution d’une portion de code programme et système sur puce correspondant Active FR3134907B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR2203873A FR3134907B1 (fr) 2022-04-26 2022-04-26 Procédé de surveillance d’une exécution d’une portion de code programme et système sur puce correspondant
US18/306,032 US12339762B2 (en) 2022-04-26 2023-04-24 Method for monitoring an execution of a program code portion and corresponding system-on-chip
CN202310460465.4A CN116956269A (zh) 2022-04-26 2023-04-26 用于监控程序代码部分的执行的方法和对应的片上系统

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2203873A FR3134907B1 (fr) 2022-04-26 2022-04-26 Procédé de surveillance d’une exécution d’une portion de code programme et système sur puce correspondant
FR2203873 2022-04-26

Publications (2)

Publication Number Publication Date
FR3134907A1 FR3134907A1 (fr) 2023-10-27
FR3134907B1 true FR3134907B1 (fr) 2026-04-17

Family

ID=83188245

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2203873A Active FR3134907B1 (fr) 2022-04-26 2022-04-26 Procédé de surveillance d’une exécution d’une portion de code programme et système sur puce correspondant

Country Status (3)

Country Link
US (1) US12339762B2 (fr)
CN (1) CN116956269A (fr)
FR (1) FR3134907B1 (fr)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3684831B2 (ja) * 1998-03-31 2005-08-17 セイコーエプソン株式会社 マイクロコンピュータ、電子機器及びデバッグシステム
DE19944991B4 (de) * 1999-09-20 2004-04-29 Giesecke & Devrient Gmbh Verfahren zur Sicherung eines Programmablaufs
CN102231130B (zh) * 2010-01-11 2015-06-17 国际商业机器公司 计算机系统性能分析方法和装置
US8365187B2 (en) * 2010-02-22 2013-01-29 Juniper Networks, Inc. Analysis of short term CPU spikes in an operating system kernel
US10496512B2 (en) * 2016-05-11 2019-12-03 Micro Focus Llc Visualization of error flows associated with errors of different types in instances of application transactions
US10503658B2 (en) * 2017-04-27 2019-12-10 Advanced Micro Devices, Inc. Page migration with varying granularity
EP3460702A1 (fr) * 2017-09-20 2019-03-27 Gemalto Sa Procédé pour détecter une attaque par injection d'erreur sur une opération sensible
US10747645B2 (en) * 2018-04-27 2020-08-18 Microsoft Technology Licensing, Llc Selectively tracing portions of computer process execution
EP3874390A4 (fr) * 2018-11-02 2022-07-06 Arizona Board of Regents on behalf of the University of Arizona Évaluation de risque adaptatif d'exécution et atténuation automatisée
US11163645B2 (en) * 2019-09-23 2021-11-02 Denso Corporation Apparatus and method of control flow integrity enforcement utilizing boundary checking
US11200119B2 (en) * 2020-01-13 2021-12-14 International Business Machines Corporation Low latency availability in degraded redundant array of independent memory

Also Published As

Publication number Publication date
US20230342279A1 (en) 2023-10-26
US12339762B2 (en) 2025-06-24
CN116956269A (zh) 2023-10-27
FR3134907A1 (fr) 2023-10-27

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