FR3137792B1 - Procédé de fabrication d’une structure semi-conductrice ou piézoélectrique - Google Patents

Procédé de fabrication d’une structure semi-conductrice ou piézoélectrique Download PDF

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Publication number
FR3137792B1
FR3137792B1 FR2206980A FR2206980A FR3137792B1 FR 3137792 B1 FR3137792 B1 FR 3137792B1 FR 2206980 A FR2206980 A FR 2206980A FR 2206980 A FR2206980 A FR 2206980A FR 3137792 B1 FR3137792 B1 FR 3137792B1
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FR
France
Prior art keywords
substrate
semiconductor
receiver
donor substrate
free surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2206980A
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English (en)
Other versions
FR3137792A1 (fr
Inventor
Cédric Charles-Alfred
Alexis Drouin
Isabelle Huyet
Stéphane Thieffry
Marcel Broekaart
Thierry Barge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR2206980A priority Critical patent/FR3137792B1/fr
Priority to TW112121112A priority patent/TW202420401A/zh
Priority to CN202380052110.XA priority patent/CN119488008A/zh
Priority to US18/881,121 priority patent/US20260020498A1/en
Priority to KR1020257003587A priority patent/KR20250029245A/ko
Priority to JP2025500104A priority patent/JP2025522633A/ja
Priority to PCT/FR2023/051048 priority patent/WO2024009046A1/fr
Priority to EP23750656.3A priority patent/EP4552443A1/fr
Publication of FR3137792A1 publication Critical patent/FR3137792A1/fr
Application granted granted Critical
Publication of FR3137792B1 publication Critical patent/FR3137792B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/08—Shaping or machining of piezoelectric or electrostrictive bodies
    • H10N30/085—Shaping or machining of piezoelectric or electrostrictive bodies by machining
    • H10N30/086—Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/09—Forming piezoelectric or electrostrictive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/50—Piezoelectric or electrostrictive devices having a stacked or multilayer structure
    • H10N30/508—Piezoelectric or electrostrictive devices having a stacked or multilayer structure adapted for alleviating internal stress, e.g. cracking control layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Micromachines (AREA)
  • Pressure Sensors (AREA)

Abstract

L’invention concerne un procédé de fabrication d’une structure semiconductrice ou piézoélectrique, comprenant les étapes successives suivantes :(a) fourniture d’un substrat donneur (11) comprenant une couche semiconductrice ou piézoélectrique (5),(b) fourniture d’un substrat receveur (12),(c) traitement d’une surface libre (7) du substrat donneur (11) et/ou d’une surface libre (9) du substrat receveur (12),(d) collage du substrat donneur (11) sur le substrat receveur (12), ladite au moins une surface traitée (7, 9) étant à l’interface entre le substrat donneur (11) et le substrat receveur (12), et (e) transfert d’une portion (3) de la couche semiconductrice ou piézoélectrique (5) du substrat donneur (11) sur le substrat receveur (12),le traitement de la surface libre (7) du substrat donneur (11) et/ou de la surface libre (9) du substrat receveur (12) comprenant les étapes successives suivantes :(c1) un polissage mécano-chimique,(c2) un retrait de matière dans une région périphérique de la surface polie (7,9). Figure pour l’abrégé : figure 9
FR2206980A 2022-07-07 2022-07-07 Procédé de fabrication d’une structure semi-conductrice ou piézoélectrique Active FR3137792B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR2206980A FR3137792B1 (fr) 2022-07-07 2022-07-07 Procédé de fabrication d’une structure semi-conductrice ou piézoélectrique
TW112121112A TW202420401A (zh) 2022-07-07 2023-06-06 用於製作半導體或壓電結構之方法
US18/881,121 US20260020498A1 (en) 2022-07-07 2023-07-07 Process for fabricating a piezoelectric or semiconductor structure
KR1020257003587A KR20250029245A (ko) 2022-07-07 2023-07-07 반도체 또는 압전 구조를 제조하기 위한 공정
CN202380052110.XA CN119488008A (zh) 2022-07-07 2023-07-07 用于制造压电或半导体结构的方法
JP2025500104A JP2025522633A (ja) 2022-07-07 2023-07-07 半導体または圧電構造体を製造するためのプロセス
PCT/FR2023/051048 WO2024009046A1 (fr) 2022-07-07 2023-07-07 Procédé de fabrication d'une structure semi-conductrice ou piézoélectrique
EP23750656.3A EP4552443A1 (fr) 2022-07-07 2023-07-07 Procédé de fabrication d'une structure semi-conductrice ou piézoélectrique

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2206980A FR3137792B1 (fr) 2022-07-07 2022-07-07 Procédé de fabrication d’une structure semi-conductrice ou piézoélectrique
FR2206980 2022-07-07

Publications (2)

Publication Number Publication Date
FR3137792A1 FR3137792A1 (fr) 2024-01-12
FR3137792B1 true FR3137792B1 (fr) 2024-10-11

Family

ID=83899501

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2206980A Active FR3137792B1 (fr) 2022-07-07 2022-07-07 Procédé de fabrication d’une structure semi-conductrice ou piézoélectrique

Country Status (8)

Country Link
US (1) US20260020498A1 (fr)
EP (1) EP4552443A1 (fr)
JP (1) JP2025522633A (fr)
KR (1) KR20250029245A (fr)
CN (1) CN119488008A (fr)
FR (1) FR3137792B1 (fr)
TW (1) TW202420401A (fr)
WO (1) WO2024009046A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3160295B1 (fr) 2024-03-14 2026-03-06 Soitec Silicon On Insulator Hétérostructure comprenant une portion exposée rugueuse d’un substrat de support

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006120785A (ja) * 2004-10-20 2006-05-11 Canon Inc 半導体層の製造方法及び基板の製造方法
US7779522B2 (en) * 2006-05-05 2010-08-24 Fujifilm Dimatix, Inc. Method for forming a MEMS
FR3045678B1 (fr) * 2015-12-22 2017-12-22 Soitec Silicon On Insulator Procede de fabrication d'une couche piezoelectrique monocristalline et dispositif microelectronique, photonique ou optique comprenant une telle couche
FR3117668B1 (fr) * 2020-12-16 2022-12-23 Commissariat Energie Atomique Structure amelioree de substrat rf et procede de realisation

Also Published As

Publication number Publication date
TW202420401A (zh) 2024-05-16
CN119488008A (zh) 2025-02-18
KR20250029245A (ko) 2025-03-04
WO2024009046A1 (fr) 2024-01-11
JP2025522633A (ja) 2025-07-15
US20260020498A1 (en) 2026-01-15
EP4552443A1 (fr) 2025-05-14
FR3137792A1 (fr) 2024-01-12

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