FR3138239B1 - Procédé de fabrication d’un substrat support pour application radiofréquences - Google Patents

Procédé de fabrication d’un substrat support pour application radiofréquences Download PDF

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Publication number
FR3138239B1
FR3138239B1 FR2207362A FR2207362A FR3138239B1 FR 3138239 B1 FR3138239 B1 FR 3138239B1 FR 2207362 A FR2207362 A FR 2207362A FR 2207362 A FR2207362 A FR 2207362A FR 3138239 B1 FR3138239 B1 FR 3138239B1
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FR
France
Prior art keywords
deposition chamber
layer
temperature
charge trapping
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2207362A
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English (en)
Other versions
FR3138239A1 (fr
Inventor
Young-Pil Kim
Chee-Hoe Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR2207362A priority Critical patent/FR3138239B1/fr
Priority to FR2210185A priority patent/FR3138240B1/fr
Priority to EP23749129.5A priority patent/EP4559018A1/fr
Priority to PCT/FR2023/051108 priority patent/WO2024018149A1/fr
Priority to US19/472,475 priority patent/US20260040907A1/en
Publication of FR3138239A1 publication Critical patent/FR3138239A1/fr
Application granted granted Critical
Publication of FR3138239B1 publication Critical patent/FR3138239B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments

Landscapes

  • Physical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

L’invention concerne un procédé de fabrication d’un substrat support comprenant une couche de piégeage de charges pour une structure de type semi-conducteur sur isolant pour application radiofréquences, comprenant : la mise en place d’un substrat de base (10) comprenant une couche (20) d’oxyde de silicium natif dans une chambre de dépôt, la montée en température de la chambre de dépôt jusqu’à une température (Tp) de dépôt de la couche de piégeage de charges (30),l’introduction d’un gaz oxydant dans ladite chambre de dépôt pour conserver la couche (20) d’oxyde de silicium natif pendant la montée en température, l’évacuation de l’oxygène de la chambre de dépôt à la température (Tp) de formation de la couche de piégeage de charges (30), le dépôt, dans la chambre de dépôt, de la couche de piégeage de charges (30) en silicium polycristallin sur la couche d’oxyde de silicium natif. Figure pour l’abrégé : Fig 1C
FR2207362A 2022-07-19 2022-07-19 Procédé de fabrication d’un substrat support pour application radiofréquences Active FR3138239B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR2207362A FR3138239B1 (fr) 2022-07-19 2022-07-19 Procédé de fabrication d’un substrat support pour application radiofréquences
FR2210185A FR3138240B1 (fr) 2022-07-19 2022-10-05 Procédé de fabrication d’un substrat support pour application radiofréquences
EP23749129.5A EP4559018A1 (fr) 2022-07-19 2023-07-18 Procédé de fabrication d'un substrat support pour application radiofréquences
PCT/FR2023/051108 WO2024018149A1 (fr) 2022-07-19 2023-07-18 Procédé de fabrication d'un substrat support pour application radiofréquences
US19/472,475 US20260040907A1 (en) 2022-07-19 2023-07-18 Method for manufacturing a support substrate for a radiofrequency application

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2207362 2022-07-19
FR2207362A FR3138239B1 (fr) 2022-07-19 2022-07-19 Procédé de fabrication d’un substrat support pour application radiofréquences

Publications (2)

Publication Number Publication Date
FR3138239A1 FR3138239A1 (fr) 2024-01-26
FR3138239B1 true FR3138239B1 (fr) 2024-06-21

Family

ID=84053308

Family Applications (2)

Application Number Title Priority Date Filing Date
FR2207362A Active FR3138239B1 (fr) 2022-07-19 2022-07-19 Procédé de fabrication d’un substrat support pour application radiofréquences
FR2210185A Active FR3138240B1 (fr) 2022-07-19 2022-10-05 Procédé de fabrication d’un substrat support pour application radiofréquences

Family Applications After (1)

Application Number Title Priority Date Filing Date
FR2210185A Active FR3138240B1 (fr) 2022-07-19 2022-10-05 Procédé de fabrication d’un substrat support pour application radiofréquences

Country Status (1)

Country Link
FR (2) FR3138239B1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6562128B1 (en) 2001-11-28 2003-05-13 Seh America, Inc. In-situ post epitaxial treatment process
JP6100200B2 (ja) * 2014-04-24 2017-03-22 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP2015228432A (ja) * 2014-06-02 2015-12-17 信越半導体株式会社 Ｓｏｉウェーハの製造方法及び貼り合わせｓｏｉウェーハ
FR3062238A1 (fr) * 2017-01-26 2018-07-27 Soitec Support pour une structure semi-conductrice
FR3079346B1 (fr) 2018-03-26 2020-05-29 Soitec Procede de fabrication d'un substrat donneur pour le transfert d'une couche piezoelectrique, et procede de transfert d'une telle couche piezoelectrique

Also Published As

Publication number Publication date
FR3138239A1 (fr) 2024-01-26
FR3138240A1 (fr) 2024-01-26
FR3138240B1 (fr) 2024-06-14

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