FR3145431B1 - Circuit de réinitialisation - Google Patents

Circuit de réinitialisation

Info

Publication number
FR3145431B1
FR3145431B1 FR2300767A FR2300767A FR3145431B1 FR 3145431 B1 FR3145431 B1 FR 3145431B1 FR 2300767 A FR2300767 A FR 2300767A FR 2300767 A FR2300767 A FR 2300767A FR 3145431 B1 FR3145431 B1 FR 3145431B1
Authority
FR
France
Prior art keywords
reset circuit
circuit
flops
flip
parity check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2300767A
Other languages
English (en)
Other versions
FR3145431A1 (fr
Inventor
Pasquale Butta'
Alessandro Inglese
Antonino Mondello
Michele Alessandro Carrano
Riccardo Condorelli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics International NV Switzerland
STMicroelectronics International NV
Original Assignee
STMicroelectronics International NV Switzerland
STMicroelectronics International NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics International NV Switzerland, STMicroelectronics International NV filed Critical STMicroelectronics International NV Switzerland
Priority to FR2300767A priority Critical patent/FR3145431B1/fr
Priority to US18/422,179 priority patent/US12449868B2/en
Priority to CN202410109300.7A priority patent/CN118413218A/zh
Publication of FR3145431A1 publication Critical patent/FR3145431A1/fr
Application granted granted Critical
Publication of FR3145431B1 publication Critical patent/FR3145431B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G06F21/554—Detecting local intrusion or implementing counter-measures involving event detection and direct action
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007—Fail-safe circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)

Abstract

Circuit de réinitialisation La présente description concerne un circuit de réinitialisation d'un dispositif électronique comprenant au moins deux composants électroniques, ledit circuit de réinitialisation comprenant : - un circuit de contrôle de parité (303) ; - au moins deux premières bascules (350) comprenant chacune une sortie reliée à moins un desdits au moins deux composants électroniques ; - au moins deux deuxièmes bascules (301-1, 301-2, 301-3) comprenant chacune au moins une sortie reliée à une entrée dudit circuit de contrôle de parité (303). Figure pour l'abrégé : Fig. 3
FR2300767A 2023-01-27 2023-01-27 Circuit de réinitialisation Active FR3145431B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR2300767A FR3145431B1 (fr) 2023-01-27 2023-01-27 Circuit de réinitialisation
US18/422,179 US12449868B2 (en) 2023-01-27 2024-01-25 Reset circuit
CN202410109300.7A CN118413218A (zh) 2023-01-27 2024-01-26 重置电路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2300767 2023-01-27
FR2300767A FR3145431B1 (fr) 2023-01-27 2023-01-27 Circuit de réinitialisation

Publications (2)

Publication Number Publication Date
FR3145431A1 FR3145431A1 (fr) 2024-08-02
FR3145431B1 true FR3145431B1 (fr) 2025-10-17

Family

ID=86604289

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2300767A Active FR3145431B1 (fr) 2023-01-27 2023-01-27 Circuit de réinitialisation

Country Status (3)

Country Link
US (1) US12449868B2 (fr)
CN (1) CN118413218A (fr)
FR (1) FR3145431B1 (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100833604B1 (ko) * 2007-01-09 2008-05-30 삼성전자주식회사 패리티 에러 검출 회로
DE102016118534A1 (de) * 2016-09-29 2018-03-29 Infineon Technologies Ag Schaltung und Verfahren zum Prüfen der Integrität eines Steuersignals
US10445500B2 (en) * 2017-06-28 2019-10-15 Arm Limited Reset attack detection
US10671763B2 (en) * 2018-11-01 2020-06-02 Nvidia Corporation Protecting circuits from hacking using a digital reset detector
US11797714B2 (en) * 2019-12-20 2023-10-24 Arm Limited Security measures for signal paths with tree structures
EP4400939A1 (fr) * 2023-01-12 2024-07-17 STMicroelectronics International N.V. Dispositif numérique ayant un circuit de tampon de réinitialisation qui peut être soumis à une attaque par pirate informatique

Also Published As

Publication number Publication date
CN118413218A (zh) 2024-07-30
US20240256018A1 (en) 2024-08-01
US12449868B2 (en) 2025-10-21
FR3145431A1 (fr) 2024-08-02

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