GB9727487D0 - Viterbi equalizer - Google Patents
Viterbi equalizerInfo
- Publication number
- GB9727487D0 GB9727487D0 GBGB9727487.2A GB9727487A GB9727487D0 GB 9727487 D0 GB9727487 D0 GB 9727487D0 GB 9727487 A GB9727487 A GB 9727487A GB 9727487 D0 GB9727487 D0 GB 9727487D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- viterbi equalizer
- viterbi
- equalizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03178—Arrangements involving sequence estimation techniques
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/01—Equalisers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2201/00—Algorithms used for the adjustment of time-domain equalizers
- H04L2201/06—Algorithms used for the adjustment of time-domain equalizers using the output of a maximum likelihood decoder (Viterbi detector)
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Error Detection And Correction (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9727487A GB2333014A (en) | 1997-12-31 | 1997-12-31 | Virerbi equalizer using dsp's |
| KR1019980043614A KR19990062535A (en) | 1997-12-31 | 1998-10-19 | Viterbi equalizer with digital signal processor processing and hardware processing |
| CN98126091A CN1230835A (en) | 1997-12-31 | 1998-12-31 | Viterbi equalizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9727487A GB2333014A (en) | 1997-12-31 | 1997-12-31 | Virerbi equalizer using dsp's |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9727487D0 true GB9727487D0 (en) | 1998-02-25 |
| GB2333014A GB2333014A (en) | 1999-07-07 |
Family
ID=10824321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9727487A Withdrawn GB2333014A (en) | 1997-12-31 | 1997-12-31 | Virerbi equalizer using dsp's |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR19990062535A (en) |
| CN (1) | CN1230835A (en) |
| GB (1) | GB2333014A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6823027B2 (en) | 2001-03-05 | 2004-11-23 | Telefonaktiebolaget Lm Ericsson (Publ) | Method for enhancing soft-value information |
| US7042937B2 (en) * | 2001-04-23 | 2006-05-09 | Koninklijke Philips Electronics N.V. | Hybrid frequency-time domain equalizer |
| US7573958B2 (en) * | 2002-07-18 | 2009-08-11 | Motorola, Inc. | Receiver for and method of recovering transmitted symbols in a H-ARQ packet retransmission |
| CN100433156C (en) * | 2002-08-15 | 2008-11-12 | 联发科技股份有限公司 | Data reading system with maximum likelihood data detection circuit in optical disk drive |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4038251A1 (en) * | 1990-11-30 | 1992-06-04 | Philips Patentverwaltung | Max probability receiver e.g. for mobile communications |
| US5390215A (en) * | 1992-10-13 | 1995-02-14 | Hughes Aircraft Company | Multi-processor demodulator for digital cellular base station employing partitioned demodulation procedure with pipelined execution |
| US5432804A (en) * | 1993-11-16 | 1995-07-11 | At&T Corp. | Digital processor and viterbi decoder having shared memory |
-
1997
- 1997-12-31 GB GB9727487A patent/GB2333014A/en not_active Withdrawn
-
1998
- 1998-10-19 KR KR1019980043614A patent/KR19990062535A/en not_active Ceased
- 1998-12-31 CN CN98126091A patent/CN1230835A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990062535A (en) | 1999-07-26 |
| CN1230835A (en) | 1999-10-06 |
| GB2333014A (en) | 1999-07-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |