HK66392A - Cache memory consistency control with explicit software instructions - Google Patents

Cache memory consistency control with explicit software instructions Download PDF

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Publication number
HK66392A
HK66392A HK663/92A HK66392A HK66392A HK 66392 A HK66392 A HK 66392A HK 663/92 A HK663/92 A HK 663/92A HK 66392 A HK66392 A HK 66392A HK 66392 A HK66392 A HK 66392A
Authority
HK
Hong Kong
Prior art keywords
cache
data
instruction
memory
instructions
Prior art date
Application number
HK663/92A
Other languages
German (de)
English (en)
Inventor
William S. Worley
William R. Bryg
Allen Baum
Original Assignee
Hewlett-Packard Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett-Packard Company filed Critical Hewlett-Packard Company
Publication of HK66392A publication Critical patent/HK66392A/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99931—Database or file accessing
    • Y10S707/99933—Query processing, i.e. searching
    • Y10S707/99934—Query formulation, input preparation, or translation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Claims (5)

  1. Un système d'ordinateur comportant une hiérarchie de mémoires à niveaux multiples et des moyens pour maintenir l'intégrité des blocs d'informations mémorisés à différents niveaux de la hiérarchie, comprenant:    un processeur (19) pour exécuter des instructions et traiter des données;    une mémoire (13) pour mémoriser des instructions et des données; un canal entrée/sortie (ou I/O) (15) relié à la mémoire (13) et à des dispositifs I/O pour transférer des données et des instructions dans la mémoire (13) et à partir de celle-ci;    un cache (21) relié entre le processeur (19) et la mémoire (13) pour mémoriser, à partir de la mémoire (13), des blocs choisis d'informations en vue d'une utilisation par le processeur (19) et comprenant des moyens indiquant réussi/manqué et comprenant un drapeau de statut valide et un drapeau de statut maculé associés à chaque bloc mémorisé;    un système d'exploitation commandant l'accès à ladite mémoire par le processeur et les dispositifs I/O;    caractérisé par un jeu d'instructions destiné à fournir une commande explicite de l'enlèvement, hors du cache (21), de blocs de données ou de l'invalidation de ceux-ci, et de la mise à jour de la mémoire à partir du cache avant que des opérations I/O ne soient exécutées, le jeu d'instructions comprenant des instructions Vider Cache de Données, Purger Cache de Données, Vider Cache d'Instructions, Vider Entrée de Cache de Données, Vider Entrée de Cache d'Instructions et Synchroniser Caches; et    l'aptitude dudit système d'exploitation à provoquer l'exécution de certaines des instructions provenant du jeu d'instructions afin de garantir la cohérence de l'information mémorisée dans le cache (21) avec l'information transférée dans la mémoire (13) ou depuis celle-ci dans le cas d'un transfert de données ou d'instructions dans la mémoire (13) ou à partir de celle-ci par l'intermédiaire du canal I/O (15); d'une modification d'une instruction dans le cache (21), ou d'une défaillance du processeur (19), grâce à quoi le bit valide, dans le cas d'une condition de réussite, est placé à "invalide" et, selon la valeur du bit maculé, l'information est enlevée du cache avec ou sans report à la mémoire.
  2. Système d'ordinateur selon la revendication 1, caractérisé en ce que, avant un transfert de données ou d'instructions dans la mémoire ou à partir de celle-ci par l'intermédiaire du canal I/O, le système d'exploitation émet des instructions Vider Cache de Données et Vider Cache d'Instructions vers le cache sur la plage d'adresses dans lesquelles, ou à partir desquelles, des données sont transférées.
  3. Système d'ordinateur selon la revendication 2, caractérisé en ce qu'il est utilisé une mémoire virtuelle (13); en ce que, lorsqu'une page ou un segment est enlevé de la mémoire (13), le système d'exploitation émet les instructions Vider Cache de Données et Vider Cache d'instructions vers le cache (21) sur la plage d'adresses de la page ou du segment; et en ce que, lorsqu'une page ou un segment est détruit, le système d'exploitation émet les instructions Vider Cache de Données et Vider Cache d'Instructions vers le cache (21) sur la plage d'adresses de la page ou du segment.
  4. Système d'ordinateur selon la revendication 2 ou 3, caractérisé en ce que le cache (21) est divisé en deux segments (41, 51), un cache de données (51) pour mémoriser des données et un cache d'instructions (41) pour mémoriser des instructions; en ce que des instructions peuvent être modifiées lorsqu'elles sont mémorisées en tant que parties d'un bloc de données dans le cache de données (51); et en ce que, après modification d'une instruction, le système d'exploitation envoie l'instruction Vider Cache de Données vers le cache (51) de données pour l'adresse du bloc comprenant l'instruction modifiée, envoie l'instruction Vider Cache d'Instructions vers le cache d'instructions (41) pour l'adresse d'une instruction modifiée et exécute ensuite l'instruction Synchroniser Caches.
  5. Système d'ordinateur selon l'une quelconque des revendications 2 à 4, caractérisé en ce que, dans le cas d'une défaillance du processeur, le système d'exploitation exécute un programme comprenant les instructions Vider Entrée de Cache de Données et Vider Entrée de Cache d'Instructions sur la plage d'index pour le cache de données (51) et le cache d'instructions (41).
HK663/92A 1985-06-28 1992-09-03 Cache memory consistency control with explicit software instructions HK66392A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/750,381 US4713755A (en) 1985-06-28 1985-06-28 Cache memory consistency control with explicit software instructions

Publications (1)

Publication Number Publication Date
HK66392A true HK66392A (en) 1992-09-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
HK663/92A HK66392A (en) 1985-06-28 1992-09-03 Cache memory consistency control with explicit software instructions

Country Status (7)

Country Link
US (1) US4713755A (fr)
EP (1) EP0210384B1 (fr)
JP (1) JPH077360B2 (fr)
CA (1) CA1270579A (fr)
DE (1) DE3681985D1 (fr)
HK (1) HK66392A (fr)
SG (1) SG72392G (fr)

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Publication number Publication date
EP0210384B1 (fr) 1991-10-16
SG72392G (en) 1992-10-02
US4713755A (en) 1987-12-15
JPS6263350A (ja) 1987-03-20
CA1270579A (fr) 1990-06-19
DE3681985D1 (de) 1991-11-21
EP0210384A1 (fr) 1987-02-04
JPH077360B2 (ja) 1995-01-30

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