HRP20131009T1 - Objekt s funkcijom virtualizacije za blokiranje funkcije naredbe za višestruke naredbe virtualnog procesora - Google Patents

Objekt s funkcijom virtualizacije za blokiranje funkcije naredbe za višestruke naredbe virtualnog procesora Download PDF

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Publication number
HRP20131009T1
HRP20131009T1 HRP20131009AT HRP20131009T HRP20131009T1 HR P20131009 T1 HRP20131009 T1 HR P20131009T1 HR P20131009A T HRP20131009A T HR P20131009AT HR P20131009 T HRP20131009 T HR P20131009T HR P20131009 T1 HRP20131009 T1 HR P20131009T1
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HR
Croatia
Prior art keywords
command
execution
function
blocking value
blocking
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HRP20131009AT
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English (en)
Inventor
Dan Greiner
Damian Leo Osisek
Timothy Slegel
Lisa Heller
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International Business Machines Corporation
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Publication of HRP20131009T1 publication Critical patent/HRP20131009T1/hr

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45541—Bare-metal, i.e. hypervisor runs directly on hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45554—Instruction set architectures of guest OS and hypervisor or native processor differ, e.g. Bochs or VirtualPC on PowerPC MacOS

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Storage Device Security (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)

Claims (6)

1. Računalna ugrađena metoda za blokiranje specifičnih funkcija za izvedbu pomoću naredbe za izvršavanje od strane logičkog procesora koju izvršava virtualni uređaj, metoda obuhvaća: postavljanje (1251) vrijednosti blokiranja naredbe (1008) definirane za virtualni uređaj, za blokiranje izvršavanja naredbe, vrijednost blokiranja naredbe ukazuje na dozvoljene funkcije; dohvaćanje (1252), pomoću navedenog logičkog procesora, naredbe (1101) za izvršavanje od strane logičkog procesora, naredba obuhvaća operacijski kod i specificira kod funkcije (1102) za množinu kodova funkcije, kod funkcije se koristi za odabir funkcije koja se treba izvesti putem naredbe, naredba je podržana jednim ili više fizičkih procesora; određivanje (1253) vrijednosti blokiranja naredbe za dohvaćenu naredbu koja ima kod funkcije, usporedbom (1253) vrijednosti blokiranja naredbe definirane za virtualni uređaj s operacijskim kodom dohvaćene naredbe; uzvratno na vrijednost blokiranja naredbe koja dozvoljava (1007, 1255) izvršavanje naredbe koja ima kod funkcije, izvršavanje dohvaćene naredbe od strane logičkog procesora; i uzvratno na vrijednost blokiranja naredbe koja ne dozvoljava (1006, 1256) izvršavanje naredbe koja ima kod funkcije, blokiranje izvršavanja dohvaćene naredbe i uzrokovanje događaja izuzeća programa.
2. Metoda u skladu s patentnim zahtjevom 1, nadalje obuhvaća: vrijednost blokiranja naredbe (1008) koja je bila definirana za virtualni uređaj za blokiranje izvođenja funkcija koje treba izvesti naredba, postavljanje vrijednosti blokiranja naredbe uzvratno na omogućavanje izvođenja virtualnom uređaju na fizičkom procesoru.; postavljanje (1351) druge vrijednosti blokiranja naredbe definirane za drugi virtualni uređaj koji se izvršava na drugom logičkom procesoru, postavljanje druge vrijednosti blokiranja naredbe uzvratno na omogućavanje izvođenja drugom virtualnom uređaju na fizičkom procesoru; i uzvratno na drugu vrijednost blokiranja naredbe koja dozvoljava (1352) izvršavanje naredbe koja ima kod funkcije, dozvoljavanje izvršavanja naredbe od strane drugog logičkog procesora; i uzvratno na drugu vrijednost blokiranja naredbe koja ne dozvoljava (1256) izvršavanje naredbe koja ima kod funkcije, blokiranje izvršavanja naredbe od strane drugog logičkog procesora.
3. Metoda u skladu s patentnim zahtjevom 1, pri čemu određivanje vrijednosti blokiranja naredbe nadalje obuhvaća korake: korištenja operacijskog koda za indeksiranje u tablici (907) za lociranje vrijednosti blokiranja naredbe definirane za virtualni uređaj, vrijednost blokiranja naredbe obuhvaća polje dozvole (1002, 1003); korištenje polja dozvole za određivanje dozvoljenih funkcija usporedbom s kodom funkcije dohvaćene naredbe; i uzvratno na funkciju koja je dozvoljena funkcija, određivanje (1007) da je izvršavanje naredbe dozvoljeno; i uzvratno na funkciju koja nije dozvoljena funkcija, određivanje (1006) da izvršavanje naredbe nije dozvoljeno.
4. Metoda u skladu s patentnim zahtjevom 1, nadalje obuhvaća korake: određivanja da li je naredba dozvoljena naredba povezivanjem operacijskog koda naredbe s vrijednosti blokiranja naredbe.
5. Računalni sustav za blokiranje specifičnih naredbi za izvršavanje od strane procesora, obuhvaća: memoriju; procesor u komunikaciji s memorijom, procesor obuhvaća element za dohvaćanje naredbe za dohvaćanje naredbi iz memorije i jedan ili više izvršnih elemenata za izvršavanje dohvaćenih naredbi; pri čemu je računalni sustav konfiguriran za izvođenje metode u skladu s bilo kojim od patentnih zahtjeva 1 do 4.
6. Računalni program koji se može unijeti u memoriju računalnog sustava iz patentnog zahtjeva 5, obuhvaća dijelove koda programa za izvođenje, kad se navedeni program izvodi na računalnom sustavu, koraka metode u skladu s patentnim zahtjevima 1 do 4.
HRP20131009AT 2010-06-24 2010-11-08 Objekt s funkcijom virtualizacije za blokiranje funkcije naredbe za višestruke naredbe virtualnog procesora HRP20131009T1 (hr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/822,368 US10521231B2 (en) 2010-06-24 2010-06-24 Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor
PCT/EP2010/067045 WO2011160723A1 (en) 2010-06-24 2010-11-08 Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor

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HRP20131009T1 true HRP20131009T1 (hr) 2013-12-06

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US (3) US10521231B2 (hr)
EP (1) EP2430532B1 (hr)
JP (1) JP5717848B2 (hr)
KR (1) KR101442382B1 (hr)
CN (1) CN102906700B (hr)
AU (1) AU2010355814B2 (hr)
BR (1) BR112012033816B1 (hr)
CA (1) CA2800640C (hr)
DK (1) DK2430532T3 (hr)
ES (1) ES2435634T3 (hr)
HR (1) HRP20131009T1 (hr)
MX (1) MX2012014529A (hr)
PL (1) PL2430532T3 (hr)
PT (1) PT2430532E (hr)
RU (1) RU2565514C2 (hr)
SG (1) SG186079A1 (hr)
SI (1) SI2430532T1 (hr)
WO (1) WO2011160723A1 (hr)
ZA (1) ZA201209646B (hr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8615645B2 (en) 2010-06-23 2013-12-24 International Business Machines Corporation Controlling the selectively setting of operational parameters for an adapter
US10521231B2 (en) 2010-06-24 2019-12-31 International Business Machines Corporation Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor
US9851969B2 (en) 2010-06-24 2017-12-26 International Business Machines Corporation Function virtualization facility for function query of a processor
US8533714B2 (en) 2011-05-03 2013-09-10 International Business Machines Corporation Dynamic virtual machine domain configuration and virtual machine relocation management
CN103309645B (zh) * 2013-04-27 2015-09-16 李朝波 一种在计算机数据处理指令中附加跳转功能的方法及cpu模块
US9582295B2 (en) 2014-03-18 2017-02-28 International Business Machines Corporation Architectural mode configuration
US9916185B2 (en) 2014-03-18 2018-03-13 International Business Machines Corporation Managing processing associated with selected architectural facilities
US10210323B2 (en) * 2016-05-06 2019-02-19 The Boeing Company Information assurance system for secure program execution
US10235138B2 (en) * 2016-09-30 2019-03-19 International Business Machines Corporation Instruction to provide true random numbers
US11226839B2 (en) * 2019-02-27 2022-01-18 International Business Machines Corporation Maintaining compatibility for complex functions over multiple machine generations
KR102657567B1 (ko) * 2019-06-04 2024-04-16 에스케이하이닉스 주식회사 인에이블 신호 생성 회로 및 이를 이용하는 반도체 장치
US11762552B2 (en) 2021-03-15 2023-09-19 Everspin Technologies, Inc. Systems and methods for NOR page write emulation mode in serial STT-MRAM

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3626427A (en) * 1967-01-13 1971-12-07 Ibm Large-scale data processing system
JPS60159948A (ja) 1984-01-30 1985-08-21 Nec Corp 命令例外処理方式
JPS62123552A (ja) 1985-11-22 1987-06-04 Nec Corp 中央処理装置割当て方式
KR930006542B1 (ko) 1990-12-31 1993-07-16 한국전기통신공사 마이크로 콘트롤러를 이용한 톤 발생장치
US5651122A (en) * 1991-05-13 1997-07-22 Motorola, Inc. Pipelined data processor that detects an illegal instruction by detecting legal instruction operation codes
ATE192246T1 (de) * 1991-09-23 2000-05-15 Intel Corp Rechnersystem mit software- unterbrechungsbefehlen, das selektiv in einem virtuellen modus arbeitet
WO1994027215A1 (en) 1993-05-07 1994-11-24 Apple Computer, Inc. Method for decoding guest instructions for a host computer
US5925125A (en) 1993-06-24 1999-07-20 International Business Machines Corporation Apparatus and method for pre-verifying a computer instruction set to prevent the initiation of the execution of undefined instructions
US5551013A (en) 1994-06-03 1996-08-27 International Business Machines Corporation Multiprocessor for hardware emulation
US5632028A (en) 1995-03-03 1997-05-20 Hal Computer Systems, Inc. Hardware support for fast software emulation of unimplemented instructions
US5790825A (en) 1995-11-08 1998-08-04 Apple Computer, Inc. Method for emulating guest instructions on a host computer through dynamic recompilation of host instructions
US5758140A (en) 1996-01-25 1998-05-26 International Business Machines Corporation Method and system for emulating instructions by performing an operation directly using special-purpose register contents
US6076156A (en) 1997-07-17 2000-06-13 Advanced Micro Devices, Inc. Instruction redefinition using model specific registers
US6009261A (en) 1997-12-16 1999-12-28 International Business Machines Corporation Preprocessing of stored target routines for emulating incompatible instructions on a target processor
US6092185A (en) 1998-04-30 2000-07-18 International Business Machines Corporation Opcode compare logic in E-unit for breaking infinite loops, detecting invalid opcodes and other exception checking
US6308255B1 (en) 1998-05-26 2001-10-23 Advanced Micro Devices, Inc. Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system
US6138229A (en) 1998-05-29 2000-10-24 Motorola, Inc. Customizable instruction set processor with non-configurable/configurable decoding units and non-configurable/configurable execution units
US6185670B1 (en) * 1998-10-12 2001-02-06 Intel Corporation System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields
US6463582B1 (en) 1998-10-21 2002-10-08 Fujitsu Limited Dynamic optimizing object code translator for architecture emulation and dynamic optimizing object code translation method
US6427202B1 (en) 1999-05-04 2002-07-30 Microchip Technology Incorporated Microcontroller with configurable instruction set
US6859870B1 (en) 2000-03-07 2005-02-22 University Of Washington Method and apparatus for compressing VLIW instruction and sharing subinstructions
US7865948B1 (en) 2001-12-03 2011-01-04 Advanced Micro Devices, Inc. Method and apparatus for restricted execution of security sensitive instructions
JP2004127255A (ja) 2002-08-02 2004-04-22 Renesas Technology Corp 情報処理装置
US20040031022A1 (en) 2002-08-02 2004-02-12 Masayuki Kabasawa Information processing device for multiple instruction sets with reconfigurable mechanism
US7257718B2 (en) 2003-05-12 2007-08-14 International Business Machines Corporation Cipher message assist instructions
US7159122B2 (en) 2003-05-12 2007-01-02 International Business Machines Corporation Message digest instructions
EP1678617A4 (en) 2003-10-08 2008-03-26 Unisys Corp COMPUTER SYSTEM PARAVIRTUALIZATION BY USING A HYPERVISOR IMPLEMENTED IN A PARTITION OF THE HOST SYSTEM
US7552426B2 (en) * 2003-10-14 2009-06-23 Microsoft Corporation Systems and methods for using synthetic instructions in a virtual machine
JP2005149361A (ja) 2003-11-19 2005-06-09 Hitachi Ltd 仮想計算機システムおよび仮想計算機システムの制御プログラム
US7493483B2 (en) 2004-02-19 2009-02-17 International Business Machines Corporation Method to prevent vulnerability to virus and worm attacks through instruction remapping
JP2005242510A (ja) 2004-02-25 2005-09-08 Matsushita Electric Ind Co Ltd 情報処理装置の命令使用権限設定方法及び情報処理装置
US20050251652A1 (en) * 2004-04-27 2005-11-10 Eswaramoorthi Nallusamy Methods and apparatus for processing an extensible firmware interface byte code instruction in a loop
US7802250B2 (en) * 2004-06-28 2010-09-21 Intel Corporation Support for transitioning to a virtual machine monitor based upon the privilege level of guest software
JP2006221606A (ja) 2005-01-17 2006-08-24 Renesas Technology Corp データプロセッサ
US8572606B1 (en) * 2005-12-29 2013-10-29 Vmware, Inc. System and method for avoiding synchronization bugs through virtualization
JP2008146542A (ja) * 2006-12-13 2008-06-26 Fujitsu Ltd マルチプロセッサシステム、プロセッサ装置及び例外処理方法
US7802252B2 (en) 2007-01-09 2010-09-21 International Business Machines Corporation Method and apparatus for selecting the architecture level to which a processor appears to conform
US8321849B2 (en) * 2007-01-26 2012-11-27 Nvidia Corporation Virtual architecture and instruction set for parallel thread computing
JP4882845B2 (ja) 2007-04-19 2012-02-22 株式会社日立製作所 仮想計算機システム
US8479195B2 (en) 2007-05-16 2013-07-02 Vmware, Inc. Dynamic selection and application of multiple virtualization techniques
US7689311B2 (en) 2007-05-29 2010-03-30 Palo Alto Research Center Incorporated Model-based planning using query-based component executable instructions
US8127296B2 (en) 2007-09-06 2012-02-28 Dell Products L.P. Virtual machine migration between processors having VM migration registers controlled by firmware to modify the reporting of common processor feature sets to support the migration
US7925923B1 (en) * 2008-01-31 2011-04-12 Hewlett-Packard Development Company, L.P. Migrating a virtual machine in response to failure of an instruction to execute
US8332846B2 (en) 2008-02-28 2012-12-11 Sony Mobile Communications Ab Selective exposure to USB device functionality for a virtual machine by filtering descriptors
US8352952B2 (en) 2008-12-01 2013-01-08 Citrix Systems, Inc. Systems and methods for facilitating virtualization of a heterogeneous processor pool
US8078854B2 (en) * 2008-12-12 2011-12-13 Oracle America, Inc. Using register rename maps to facilitate precise exception semantics
US8195923B2 (en) 2009-04-07 2012-06-05 Oracle America, Inc. Methods and mechanisms to support multiple features for a number of opcodes
US9851969B2 (en) 2010-06-24 2017-12-26 International Business Machines Corporation Function virtualization facility for function query of a processor
US10521231B2 (en) 2010-06-24 2019-12-31 International Business Machines Corporation Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor

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HK1180804A1 (zh) 2013-10-25
BR112012033816A2 (pt) 2018-05-15
JP5717848B2 (ja) 2015-05-13
ES2435634T3 (es) 2013-12-20
DK2430532T3 (da) 2013-11-25
CN102906700A (zh) 2013-01-30
RU2012149006A (ru) 2014-05-27
RU2565514C2 (ru) 2015-10-20
KR20130060233A (ko) 2013-06-07
US20190361701A1 (en) 2019-11-28
SG186079A1 (en) 2013-01-30
BR112012033816B1 (pt) 2020-12-01
EP2430532A1 (en) 2012-03-21
AU2010355814B2 (en) 2014-05-15
WO2011160723A1 (en) 2011-12-29
US20110320773A1 (en) 2011-12-29
SI2430532T1 (sl) 2014-02-28
US20210255867A1 (en) 2021-08-19
CA2800640A1 (en) 2011-12-29
JP2013535063A (ja) 2013-09-09
AU2010355814A1 (en) 2012-12-20
ZA201209646B (en) 2013-08-28
KR101442382B1 (ko) 2014-09-17
US11809870B2 (en) 2023-11-07
PL2430532T3 (pl) 2014-04-30
US11086624B2 (en) 2021-08-10
MX2012014529A (es) 2013-01-29
EP2430532B1 (en) 2013-10-16
CN102906700B (zh) 2015-11-18
US10521231B2 (en) 2019-12-31
CA2800640C (en) 2017-12-12
PT2430532E (pt) 2013-11-25

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