IE860793L

IE860793L - Selectively accessible memory having active load

Info

Publication number: IE860793L
Application number: IE860793A
Authority: IE
Original assignee: Philips Nv
Priority date: 1985-03-29
Filing date: 1986-03-26
Publication date: 1986-09-29
Also published as: DE3674613D1; JPS61224193A; EP0196715B1; FR2579816A1; EP0196715A1; CA1259135A; KR940009080B1; IE58879B1; AU584404B2; AU5530986A; KR860007665A

Abstract

1. A selectively accessible memory (RAM) having an active load for storing binary information and comprising a plurality of cells organized in lines and columns, each cell comprising a first and a second transistor of the NPN type each comprising on the one hand a first and a second emitter, the first emitters being connected to each other and the second emitters being each connected to a column selection conductor, and on the other hand a base connected to the collectors of a third and a fourth transistor, respectively, of the PNP type, and finally a collector connected to the bases of the third and the fourth transistor, respectively, the collector of the third transistor being connected to the base of the fourth transistor and conversely, while the emitters of the third and fourth transistors are connected to each other and to a line selection conductor and comprise a diode (D1, D2) in parallel to the emitter-base junction of the third (T3a, T3b, ...) and fourth (T4a, T4b, ...) transistors of each cell and having the same direction as the said junction, characterized in that, in order to reduce the inverse current of the non-selected cells, the said diode (D1, D2) is formed by the collector-base junction of a shunt transistor (T5b, T6b) of the NPN type whose emitter and base ar mutually short-circuited and connected to the said line selection conductor. [EP0196715A1]

Description

58879 1 Active load random access memory.

The invention relates to a selectively accessible memory (RAM) having an active load for storing binary information and comprising a plurality of cells organized in lines and columns, each cell comprising a first and a second transistor of the HPN type each 5 comprising on the one hand a first and a second emitter, the first emitters being connected to each other and the second emitters being each connected to a column selection conductor, and on the other hand a base connected to the collectors of a third and a fourth transistor, respectively, of the PHP type, and finally a collector connected to the 10 bases of the third transistor being connected to the base of the fourth transistor and conversely, while the emitters of the third and the fourth transistors are connected to each other and to a line selection connector and comprise a diode in parallel to the emitter-base junction of the third fourth transistors of each cell and having the same 15 direction as the said junction.

Semiconductor memories of the type indicated are well known to those skilled in the art both as to their general organization and as to the operation of each of the elementary cells in which the information is stored in the form of two possible conductions states, 20 i.e. one conduction state in a half-cell (for example first and third transistors), this state imposing the blocked state of the other half-cell associated with it (in this case second and fourth transistors).

A cell of the type comprising complementary transistors is described in US-PS No. 4,257,059.

It is known that, when a half-cell is connected in the forward direction, the two complementary transistors of this half-cell -are saturated at the point at which the product of their respective amplifications is equal to 1. This holds independently of the value of the current which flows through it so that even at the low current 30 levels used for maintaining the information, of the order of a few microamperes, the transistors of the half-cell concerned are still strongly saturated. 8879 2 The saturation phenomenon involves a disadvantage, which will be explained in greater detail. In the following description, lor the sake of simplicity and with reference fco common practice, the first and second transistors of the first conductivity type (multi-emitter transistors) are chosen to be of the NPN type and the transistors of the second type are PHP transistors.

Among a column of cells, the selection of a particular cell, for example with a view to a reading, is considered. This selection has been determined by an increase of the voltage of the line selection conductor, which is connected to this particular cell. Inside this particular cell, one of the half-cells is in the on-condition so that the corresponding read-write conductor or column selection conductor has also its potential increased because the second emitter of its NPN transistor (for example the first transistor) gives up the selection current at this read/write conductor. The other cells of the same column which are not selected at this instant are only subjected to the hold current. Some of these other cells have their half-cells in the on-state on the same side as the particularly selected cell. The second emitter of their first NPN transistor, as should be borne in mind, is connected to the same read/write conductor. From this it follows that for these other cells of the column each second emitter is polarized in the reverse or forward direction at a voltage less than a diode direct voltage (Vj^ ). These transistors operate in the inverse mode, because the first emitter brings them into saturation and hence opens their base/collector junction. This results in an undesired inverse current, which flows in these emitters, which act as collectors.

In addition to the fact that the said inverse current can increase for a single cell to a substantial fraction of the value of the hold current, which involves the risk of seriously disturbing the operation of this cell, this, current is also cumulated along a read/write conductor and can thus be multiplied by a number which can reach the number of cells (minus one) contained in a column. In the case of memories of high capacity, the overall leakage current in a column can thus become a non-negligible fraction of the selection current itself, thus causing considerable disorders especially at the level of the peripheral read/write circuits.

Moreover, the value of the said inverse current depends upon the value of the inverse amplification of the NPN- transistors, which inverse amplification can be mastered only with difficulty in practice and can fluctuate from one production series to another.

European Patent 029 717 discloses a static memory of the o» bipolar type having complementary transistors and a diode in parallel to the emitter-base junction of the third and fourth transistors of each 4, call. This diode, in this case pn', is formed by the junction between the bottom of a p-type zone and a buried layer of the n~ type.

Such a diode renders it possible to avoid the charge 10 storage effect in the diode and to obtain a certain degree of immunity to high noise. Nevertheless, such a device entails the disadvantage of a high parasitic capacitance which has the effect of considerably increasing the transistion time from the blocked state to the saturated state of the first and second HPN transistors, which diminishes the 15 speed of the cell.

The invention has for its object to meet to a great extent the difficulties mentioned above, without disturbing the functioning of the cell, particularly in as far as its speed is concerned.

A selectively accessible memory acording to the invention is characterised in that, in order to reduce the inverse current of the non-selected cells, the said diode is formed by the collector-base junction of a shunt transistor of the NPN type whose emitter and base are mutually short-circuited and connected to the said line selection 25 conductor.

A diode of this type, which is known per se from, for example, Bipolar and MOS Analog IC's by h. Grebene, p. 125, has the additional advantage that it is faster than the PNP transistor with which it is associated, which renders it possible to quickly release the 30 charges stored in the transistor base in the saturated state, thus increasing cell speed.

The cell modification according to the invention as defined above is not only compatible with the improvement known per se «* from British Patent GB 1,405,285 (Ferranti) in the fairly different 35 context of the cells having a resistive load, but it also permits of % obtaining with this improvement a cumulation of effects on the inverse current. The said improvement consists, as should be borne in mind, in that the first and* second transistors of each cell are provided wilth a third emitter short-circuited with the base of the corresponding transistor. This does not reduce the overall value of the inverse current in the half-cell concerned, but a substantial part of the latter <9 is generated from the base current of the corresponding transistor . reducing accordingly the undesired current in the column conductor.

V' , According to an embodiment of the invention, each of the first and second multi-emitter transistors of each cell is a vertical transistor, whose collector is constituted by a buried layer and whose 10 base is constitued by a first surface adjacent region in which the said emitters are provided, each of the third and fourth transistors of each cell is a lateral transistor, whose collector is constituted by the said first surface adjacent region and whose emitter is constituted by a second surface adjacent region .separated from the first.surface adjacent 15 region by a first narrow surface adjacent portion which prolongs locally at the surface the buried layer and constitutes the base of the lateral transistor, and the shunt transistor is a second vertical transistor, whose emitter region is a second vertical transistor, whose emitter region is provided in the second surface adjacent region, which 20 constitutes its base and whose colector is constituted by the said buried layer. This embodiment permits of using the invention without enlarging the dimensions of the cells.

The emitter region of the second vertical transistor can be disposed at least in part under the selection conductor, which thus 25 ensures the short-circuit between its emitter and its base.

The invention will be more clearly understood when reading the following description given by way of non-limitative example in connection with the drawings, in which: Fig. 1 shows a diagram of the arrangement of the cells 30 inside a memory according to the prior art, Fig. 2 shows an electric circuit diagram of a cell according to the invention, and Fig. 3 shows a diagram of the latter incorporating the © said known improvement, - Figures 4 and 5 show two variations of the electric 0 circuit diagram of the invention, Fig. 7 incorporating the said known improvement, Figures 6 and 7 shown in plan view and in vertical sectional view AA, respectively, an embodiment of the circuit diagram of Figures 4 and 5.

Fig. 1 shows a diagram of a part of a semi-conductor 5 memory according to the prior art. The rectangles 1a, 1b, 1c .. . each represent one of the cells of a column, while the rectangles 2a, 2b and ^ 2c ... represent the cells of the following column. The cells of a line, 1a, 2a, ..., are connected in parallel between a line selection conductor 10a and a hold current source 20a. Likewise, the cells 1a, 2b, 10 ... of the following line are connected between a line selection conductor 10b and a hold current source 20b. The same holds for the following lines of cells, such as 1c, 2c ..., the line selection conductors, such as 10c, and the hold current sources, such as 20c.

With regard to the cell la, the elements constituting a 15 cell are shown, i.e. a first transistor T^a of the NPN type having two emitters, the first of these two emitters designated as "hold emitter" being connected to the hold current source 20a. The base and the collector of the transistor T^a are connected to the collector and the base, respectively, of the transistor T-ja of the PNP transistor 20 T^a is connected to the line selection conductor 10a. The second emitter designated as "selection emitter" of the transistor T^a is connected to a read/write conductor 15 for reading and writing the memory. The assembly formed from the transistors T^a and T^a constitutes a first half-cell, while a transistor T2a of the HPN type 25 having two emitters is associated with a transistor T^a of the PHP type in order to form a second half-cell identical to the first half-cell. These two half-cells are thus connected in parallel between the line selection conductor 10a and the hold current source 20a. The first and second half-cells are connected to each other in known manner by 30 cross-coupling, the base and the collector of the transistor T The other cells of the memory are constituted by similar elements. Inside the cells 1b and 1c, only the NPN multi-emitter transistors T^c and "^2h' T2C are shown, whose operation is similar to that of the transistors Tla and respectively.

The conductors 15 and 16 of the first column have 5 connected to them the read/write transistors T^ and respectively, associated with this column. Likewise, for the following columns, such as represented by the cells 2a, 2b, 2c..., other read/write transistors are connected to the column conductors, which transistors are represented by T.^ an^ ^162 the Figure. In the 10 assembly of the transistors T151' T152 *"" ., the bases are connected to each other and this also holds for the collectors. A similar arrangement is utilized with regard to the assembly of the transistors T161• T1S2 * * • ' By means of the numerical values indicated in a practical embodiment, the difficulty arising with the use of such a memory according to the prior art will now be precisely defined, which difficulty will be met in accordance with the invention.

It is assumed that the line 10a is selected and that attempts are made to read the column 1a, 1b, 1c by means of the 20 conductors 15 and 16. Let it further be assumed that at this instant, all the half-cells are in the oa-state on the left-hand side of the Figure, that is to say that the transistors T1a' T3a' T1b' T1c are conducting (the base of T-ja, ... is at the high level H and that of T2jj ... is at the low level L). According to common practice in ECL technology, the high level H is at -1.6 V and the low level L is at -2.4 V.

The hold currents per half-cell have been chosen to be about pA, while the reading current is ensured to be of the order of 1000 30 pA. The selection conductors 10b, 10c of the non-selected conductor 10a is brought to a potential of -1.6 V. The column conductor 15 is at -2.4 V, i.e. 0.8 V lower than H, this voltage drop essentially being represented by the of the transistor T^a, whose emitter feeds current to the column conductor 15. The reading level —is 35 present at the base of the transistor T^-j.

The voltage of the line selection conductors 10b and 10c of -2.6 V is returned with a slight voltage drop to the base of the transistor and to that of the transistor T^c because hypothetically these transistors are in an on-state by their hold emitters. Since the transistors and T^c are otherwise in a saturated state produced by the hold current given up by their hold 5 emitters, their base/collector junctions are polarized in the proximity of the forward direction of these junctions.

The unfavourable conditions are then combined in orer that the transistors and T^c operate in the inverse mode, i.e. this time unsaturated, at the level of their selection emitters t>2> 10 that is to say that the functions of the selection emitters ^ and of the collectors are inverted with respect to their usual polarization.

It can be ascertained that in practice an undesired "inverse"' current effectively enters into the selection emitter E2 of each of the transistors and T^c, the value of this current being 15 of the order of several pA per emitter. Besides the fact that at the level of a cell this current is not negligible with respect to the hold current and can adversely affect the operation of the associated PMP transistors due to the fact that the latter should operate at a current considerably smaller than expected, the inverse currents of the cells 20 1b, 1c etc. of the same column are added at a column conductor, such as the conductor 15. In the case of memories of high capacity having, for example, 64 cells per column, the sum of the inverse current can become a non-negligible fraction of the selection current itself, thus involving serious disturbances of the operation of the read/write 25 circuits of a column.

Fig. 2 shows a particular cell denoted by 1b, which is none other than the cell lb of Fig. 1 modified in order to illustrate the invention, the corresponding elements of the prior art arrangement being indeed provided with the same reference numerals. According to the 30 invention, a diode (D^,D2) is connected in parallel in each of the emitter-base paths of the transistors and respectively, and in the same direction. In other words-, for transistors and of the PNP type the diodes and D2 are connected in forward direction between the line selection conductor 10b and the bases of the 35 said transistors.

It could be supposed a priori that this adjunction would be counter-effective due to the fact that these diodes and D21 because they derive current that has to flow through the transistor, have the effect that the amplification decreases, the associated assembly of diode and transistor having in fact an amplification which is substantially lower than the transistor alone and 5 is the lower as the diode derive more current. j The invention is first based on the fact that, whilst the 1 ... > product of the amplifications of the two transistors remains sufficiently higher than 1, it is possible to maintain the stability of the cell.

The second important point is that the Application has found that the parameter directly determining the value of the reverse current is not a current parameter, as in the case of the prior art, but a voltage parameter: the value of the collector/base voltage '^bc of the transistor T^ or dependent upon the condition of the cell, is concerned and the variation of the reverse current is very quick (division by two for a reduction of the voltage of 18 mV).

The third important point is that the fact is utilized that, if, for example, the transistor is traversed by the said reverse current, the other transistor of the same half-cell is in 20 the saturated state. In this case, the diode produces a derivation of the emitter current I£ from the transistor T-jj, and the emitter/base voltage decreases (by 18 mV for a division by two of the current Ic).

The emitter/collector voltage Vce, which is already low 25 (of the order of 50 mV) , also decreases, but by an amount smaller than the decrease of the V^e of because the saturated state of the transistor T-jj, is only slightly modified. The voltage of the collector of the transistor being smaller than that of its base (the base/collector junction is almost opened), the collector/base of 30 the transistor decreases, which leads to a decrease of the leakage current.

A diode D-. is taken by way of example, which derives 60-. of the emitter current from the transistor i.e. a division A of the current Ig by 2.5, the base voltage of T2^ increases by 25 35 mV, like that of the collector and the voltage of the collector of T2k increases only by 10 mV, like that of the base of T^.

Roughly, the volgtaye "v^ of the transistor T^ decreases by 25 - 10 = 15 mV. This leads to a reduction of the leakage current in a ratio approximately equal to 1.79.

According to Fig. 3, the transistors and 12^ are each provided with a third emitter and E'^, respectively, shortcircuited with the base, as is shown Per se from British Patent GB 1,405,285 (Ferranti) mentioned above. In a remarkable manner, a v cumulation is obtained of the results provided by the diodes and D2 on the one hand and by the emitters E-j and E'3 on the other hand. In fact, as has been stated above, the col lector/base voltage 10 Vbc of the transistors and Tjjj is determinative of the value of the leakage current. The supplementary emitter Ej supplies, if the left-hand half-cell is saturated, a part of the leakage current, for example 50% thereof, if the emitters and E^ have the same surface area, the overall value of the leakage current remaining the same as in 15 the case of Fig. 2. In the above example, the leakage current in the column conductor 15 is further divided by two with respect to the case shown in Fig. 2.

According to Figures 4 and 5, in which the same elements are provided with the same reference symbols as in Figures 2 and 3, the 20 diodes and D2 are constituted, according to the invention, by the collector/base junction of the transistors T5b and T6b' respectively, of the type opposite to that of the transistors 13^ and The emitter and the base of the transistors and are shortcircuited and connected to the line selection conductor 10. The 25 collector of the transistors and Tgj, is connected to the base of the transistors T^ and respectively. The transistors and are of the ?NP type and their desaturation is facilitated to a great extent by the presence of the collector/base junction of the transistors and T^, which is intrinsically quicker.

According to Figures 6 and 7, each half-cell is realised at a surface of a substrate 50 in an insulating island 51 and 52, respectively, limited by an insulating layer 33 consisting, for example, of Si02- The island 51 comprises, for example, in the case of a , substrate of the £ -type, a highly M^-doped contact layer forming the 35 bottom of the island 51 on which is disposed a semi-conducting buried , layer 34 which is N-doped and forms the collector of the transistor At the surface are provided: a first surface adjacent region 36 of the pr type constituting the base of the transistor comprising emitter regions E^, E2 and, as the case may he, E3 of the nr-type; and a second surface adjacent region 35 which is also of the p+-type and is separated from the first 5 region by a first surface adjacent narrow portion 31 prolonging the buried collector layer 34 locally at the surface.

In other words: the transistors T^ and (E^, ^2' £31 36, 34) are vertical and the transistors and (35, 31, 36)" are lateral.

Fig. 6 shows more particularly how the metallizations are disposed.

It should be noted that the drawing of Figures 6 and 7 are only diagrammatic and that for the sake of clarity the proportions are arbitrarily not taken into account. In these Figures, certain 15 insulating surface layers are not shown. For the sake of simplicity, the metal strips serving as contacts on the various regions of the semiconductor body are shown to be narrower than the corresponding regions, whereas in practice they are realized to be wider than the contact windows and partly bear on an insulating layer. 20 Consequently, with reference to Fig. 6, it should be noted that the buried layers 30 and 40, which extend beneath the islands 51 and 52, respectively, are prolonged under collector contact points C and C . The deep oxide 33 has in fact such a thickness that a considerable part of the buried layer subsists in the zones in which 25 both islands are simultaneously formed, especially in the said collector contact zones C and C.

The emitter is made in two parts, a hold current source conductor 11 interconnecting the emitters and E'^ of the cells of the same line insulated from the base region 36 between these 30 two parts by an insulating layer of, for example, oxide. This measure is known from French Patent No. 2,413,782 in the name of the Applicant.

The other line interconnection 10 is obtained by a line selection conductor connecting electrically the emitter regions 35 and 45 of the cells of the same line.

The column connections are obtained by the column selection metallizations 25 and 26, which interconnect the emitters E2 of the same column for the metallization 25 and the emitters E'2 of 11 the same column for the metallization 26.

The internal electrical connections of the cell are obtained by metallizations 130 and 140. The metallization 130 connects the base 36 of the transistor to the collector C' of the 5 transistor and the metallization 140 connects the base 45 of the transistor to the collector C of the transistor T^.

The emitters E3 and E'3 that may be present are disposed beneath regions 133 and 143 of the metallizations 130 and 140, which short—circuit them with the basse 33 and 46, respectively, of the 10 transistors and Tjjj. The emitter regions £3 and E' 3 are generally narrower than the regions 133 and 143, which project on either side at 131 and 132, and 141 and 142, respectively.

Consequently, the operation of the transistors T1b and Tjv, is not disturbed with regard to their emitters and Ejj, by 15 their base resistance pinched by the supplementary emitter E3.

The transistors T^ and Tg^ are vertical transistors, whose emitter is constituted by a region of the nTtype 135 and 145, respectively, whose base is constituted by the regions 35 and 45, respectively, that is to say the emitter of the transistors T^ and 20 T^jj, and whose collector is constituted by the afore-mentioned regions 34 and 30. The regions 135 and 145 are situated at least in part beneath the metallization 10, which realized the emitter-base short-circuit of the transistors T^ and Tg^,- Preferably, the regions 135 and 145 axe situated completely beneath the metallization 10 under the same 25 conditions as the emitter regions E-j and £'3. They occupy a fraciton of the surface of the regions 35 and 45 and their doping may advantageously be the same as that of the emitter regions to E3.

The method of.realizing a semiconductor memory integrating a plurality of cells as described in Figures 6 and 7 does 30 not involve particular difficulties and utilizes the known techniques used in the manufacture of integrated circuits with lateral insulation by deep oxide, especially ECL circuits. For example, reference may be made to the information given in the French Patent Applicatin No.2,413,782 already mentioned and incorporated by way of reference in 35 the present case as to general manufacturing techniques.

When a self-alignment method should be used and especially the contact windows of the emitters at the same time serve (<' 12 for the ion implantation of these emitters, it lias to be ensured that for forming emitters or supplementary regions a window having the width of the base contact is provided, then the latter is reduced by a mask of photosensitive lacquer to the dimensions desired for the emitter or the 5 supplementary regions and subsequently its implantation is effected.

When the lacquer mask is withdrawn, a base contact window is obtained ■'i whrch includes the emitter or the supplementary region. When a conductor is used which projects on all sides at the periphery of the contact windows, it is ensured that the short-circuit aimed at between the base 10 and the supplementary emitter is obtained. 13

Claims

1. CLAIMS; 1„ A selectively accessible memory (RAM) having an active load for storing binary information and comprising a plurality of cells organised in lines and columns, each cell comprising a first and a second 5 transistor of the HPH type each comprising on the one hand a first and a second emitter, the first emitters being connected to each other and the second emitters being each connected to a column selection conductor, and on the other hand a base connected to the collectors of a third and a 10 fourth transistor, respectively, of the PHP type, and finally a collector connected to the bases of the third and the fourth transistor, respectively, the collector of the third transistor being connected to the base of the fourth transistor and conversely,, while the emitters of the third 15 and fourth transistors are connected to each other and to a line selection conductor and comprise a diode (Dl, D2) in parallel to the emitter-base junction of the third (T3a, T3b, »«.) and fourth (T4at, T4b, .«„) transistors of each cell and having the same direction as the said junction, 20 characterized in that the said diode (Dl, D2) is formed by the collector-base junction of a shunt transistor (T5b, TSh) of the HPN type whose emitter and base are mutually short-circuited and connected to the said line selection conductor. 25

2. A memory as claimed in Claim 1, characterized in that the first transistors (Tla, T2a and second transistors (T2a, T2b „ „ „) of each cell are each provided with a third emitter (E3, E13) short-circuited with the base of the corresponding transistor. 30

3. A memory as claimed in Claim 2, characterized in that each of the first and second multi-emitter transistors (Tla, T2a, Tib, T2b of each cell is a vertical transistor, whose collector is constituted by a buried layer (34) and whose base is constituted by a first 35 surface adjacent region (36), in which the said emitters 14 (El*. „E3) .are formedj, in that; each of the third and fourth transistors (T3at, T4af T3b, T4b„»„) of each cell is a lateral transistor, whose collector is constituted by the first surface adjacent region (35)f whose emitter is 5 constituted by a second surface adjacent region (35);separated from the first region by a first surface adjacent narrow portion (31) prolonging the buried layer (34);locally at the surface and which constitutes the base of the lateral transistor*. and in that the shunt transistor 10 (T5hf TSfa) is a second vertical transistor, whose emitter region (135) is formed in the second surface adjacent region (35) , which constitutes its base{, and whose collector is constituted by the said buried layer (34) .

4. A memory as claimed in Claim 3 characterized 15 in that the emitter region (135) of the second vertical transistor (T5b, T6b) is disposed at least in part under the line selection conductor (10) , which thus ensures that a short-circuit between its emitter (135) and its base (35) is obtained™ 20

5. A selectively accessible memory according to claim 13 substantially as hereinbefore described with reference to Figures 2 and 3S or 4 to 7 of the accompanying drawings. Dated this 26th day of March, 1986. BY: TOMKINS & CO.9 Applicants' Agents, (Signed) 5 Dartmouth Road9 Dublin

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