IES69859B2 - Test apparatus - Google Patents

Abstract

A test apparatus comprises a test device (13) for measuring an electrical characteristic of a device under test (16) and a digital control device (PC 11) connected to the test device by a bus (12) for remotely controlling and receiving test results from the test device. The test device (13) includes a digital memory (21) readable and writable by the control device via the bus and containing calibration data established during a calibration run in which the test device tests at least one device whose electrical characteristic is known. The digital control device uses the calibration data to adjust the results of live testing .

Description

TEST APPARATUS The present invention relates to a test apparatus for measuring at least one electrical characteristic of a device under test (DUT).

A test apparatus is known in which a personal computer (PC), acting as a digital control device, remotely controls a test device for measuring an electrical characteristic, for example ground resistance, of a DUT.

A problem with such apparatus is that the test results received from the test device can depend on variable characteristics of the test device itself, for example, the impedence of leads connecting it to the DUT. Thus, different PCs connected to different test devices often need different configurations of the control program installed to compensate for these variable characteristics. It is a time consuming task to configure the PC when it is used with different test devices.

It is an object of the invention to mitigate this problem.

Accordingly, the invention provides a test apparatus comprising at least one test device for measuring an electrical characteristic of a DUT and a digital control device connected to the test device by a bus for remotely controlling and receiving test results from the test device, wherein the test device includes a digital memory readable and writable by the control device via the bus and containing calibration data established during a calibration run in which the test device tests at least one device whose electrical characteristic is known, and wherein the digital control device uses die calibration data to adjust the results of live testing.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, wherein: Fig. 1 is a schematic view of a test apparatus according to the invention, and -2Fig. 2 is a block diagram of the EC adapter of Fig. 1.

The test apparatus 10, Fig. 1, comprises a PC 11 which runs a control program which communicates through a daisy chained bus 12,12', 12 with a plurality of test devices of which the first two in the chain are shown at 13, 14. Each test device such as 13, 14 is connectible via a respective set of leads 15 to an electronic or electrical DUT 16.

The embodiment uses EC bus technology which was developed by Philips for simple inter IC control. As is well known, the IIC bus is a bidirectional 2-wire bus of which one wire (the SCL line) carries serial clock signals and the other wire (the SDA line) carries serial data signals.

All EC bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the HC bus.

In the present embodiment, therefore, the bus 12, 12', 12 is an EC bus. In order for the PC 11 to communicate with die test devices 13 and 14 on the bus, it must be able to send and receive commands on an IIC interface.

Since PCs do not usually contain an IIC interface built in, an IIC adapter 9 is plugged into the PC parallel communications port LPT1.

In the adapter 9 connection is made to four of the parallel port pins as seen in Fig. 2. The PC 11 can, through software, monitor and change die states of individual port signals on the parallel port. In this way, the PC 11 can toggle and monitor the send and receive signals on the port to emulate the operation of the HC signals SDA and SCL. Open collector drivers 25 are required because EC is a multi-user, multi-master bus, with many devices capable of being connected simultaneously to the same signals.

The IIC bus standard limits the cable length to about 0.5 meters. In order V to avoid this restriction die adapter 9 includes an EC buffering device 26 (Philips Components Type P82B715P) to convert the standard EC bus into ’ a buffered EC bus which can send and receive signals over a much greater distance than the standard EC bus. However, this requires a similar device at the other end of die buffered EC bus 12 to convert the buffered signals back to the standard EC signals once more for use by the test device 13. -3Thus, returning to Fig. 1, the test device 13 has a similar HC buffer 18 at the other end of the buffered HC bus 12, which converts the signals to standard form for interfacing with a standard IIC bus 22 in the test device 13. The bus 12* between the test devices 13 and 14 is also a buffered HC bus which connects to a further IIC buffer 18 in the test device 14, and so on along the daisy chain.

In the present embodiment, the first test device 13 comprises a model M100 DC Hipot Tester 23 and the second device 14 comprises a model M25 Ground Tester 24, both manufactured by ROD'L, USA. The M100 Hipot Tester 23 applies a high voltage to the DUT 16 and measures the resultant current flowing. The M25 Ground Tester 24 on the other hand measures the ground resistance of the DUT 16.

Both testers 23, 24 include an expansion slot into which a respective interface card 17 is inserted. For convenience, in Fig. 1 each card 17 is shown outside its respective tester 23, 24, but in practice it will be contained within the external housing of the tester, as will the respective HC buffer 18. Each interface card 17 comprises a number of HC bus compatible IC devices including at least one digital-to-analog and analog-to-digital I/O chip 19 (Type PCF8591) and at least one digital I/O chip 20 (Type PCF8574).

The chips 19 provide for the sending and receiving of analog data to and from the tester 23 or 24, while the chips 20 provide for the sending and receiving of digital data to and from the tester 23 or 24, all under the control of the PC 11 which communicates with the card 17 via the standard DC bus 22. The number of chips 19, 20 on each card 17 is determined by the number of analog and digital I/O lines to the respective tester 23 or 24. In the present embodiment the M100 interface card includes one PCF8574 chip 19 located at address 46H and four PCF8591 chips 20 located at addresses 94H, 96H, 98H and 9AH respectively, and the M25 interface card includes two PCF8574 chips 19 located at addresses 40H and 42H respectively and one PCF8591 chip 20 located at address 92H.

In addition, each interface card 17 includes an IIC bus compatible -4addressable EEPROM chip 21 (Type PCF8582) with a capacity of 256 bytes. On the M100 interface card the EEPROM chip 21 is located at address A4H, while on the M25 interface card the EEPROM chip 21 is located at address A2H. As will be described, these EEPROM chips 21 store calibration information for their respective testers 23 and 24.

Each HC bus compatible device 19, 20, 21 has an 8-bit address. As is standard in EC technology, the lowest three bits correspond to three external pins on the device which may be tied high or low to change the device address, while the remaining upper five bits are internally pre-programmed.

The PC 11 switches the data signal line SDA (Fig. 2) with each clock signal line SCL pulse, to transmit address and command information across the bus 12. Each device 19, 20, 21 monitors the signal lines SCL, SDA to determine if it is being addressed by the PC. After an address byte, the next byte on the SDA line will either be data for the device or a further internal address for the device. Thus, if an EEPROM 21 is addressed, then the next byte of information will hold the address for the word to be read or written in the EEPROM. The following byte will then contain information to he read from or written to the EEPROM depending on the mode of access. If, however, an I/O device 19 or 20 is addressed, then the byte after the address byte will contain a command, instructing the tester 23 or 24 to set its outputs or return the status of its input lines.

Prior to live use a calibration run is performed in which the testers 23 and 24 are instructed by the PC 11 to determine the characteristics of a series of known circuits. The respective offsets between the expected results and the actual results are then written to the EEPROM 21 by the PC 11. Each test device 13,14 therefore contains its own calibration information. r In normal use for live testing, the PC 11 control program issues commands < over the bus 12,12', 12 to remotely start a tester 23,24, set up test parameters, and receive the test results in a conventional manner.

When the PC control program receives a test result back from a test device -513, 14 it reads the offset data from the respective EEPROM 21 and carries out a linear interpolation to determine the probable error of the result received from the tester and corrects the result accordingly.

Although the embodiment of the invention has been described in terms of a bus using EC technology, the invention could be implemented using other bus protocols, such as GPIB, RS232 or IEE488. Also the invention is not limited to the particular testers (M25, Ml00) described.

Claims (5)

1. A test apparatus comprising at least one test device for measuring an electrical characteristic of a DUT and a digital control device connected to the test device by a bus for remotely controlling and receiving test results from the test device, wherein the test device includes a digital memory readable and writable by the control device via the bus and containing calibration data established during a calibration run in which the test device tests at least one device whose electrical characteristic is known, and wherein the digital control device uses the calibration data to adjust the results of live testing.

2. A test apparatus as claimed in claim 1, wherein the bus is a buffered IIC bus.

3. A test apparatus as claimed in claim 2, wherein the digital control device is a programmed personal computer which communicates with the bus through an HC adapter connected to a parallel communications port of the control device.

4. A test apparatus as claimed in claim 1, 2 or 3, including a plurality of test devices daisy chained to the bus.

5. A test apparatus substantially as described with reference to die accompanying drawings.