IES980710A2 - Memory Addressing - Google Patents

Abstract

An ASIC circuit device microprocessor interface (10) has a UPI (17) which interfaces between external ports (18-21) and internal access registers (11). The access registers are connected to a RAM port controller (12(c)) and an internal register access controller (12(a)). These controllers interface between the access register (11) and the relevant memory or registers. Reads and writes are performed by an external processor (2) using the access registers (11).

Description

''Memory Addressing The invention relates to memory addressing and/or register addressing, and particularly to internal or external addressing of memory and/or registers associated with a dedicated circuit such as an ASIC or an FPGA device.

Generally, such devices are connected to a microprocessor interface to allow the microprocessor access internal or external memory or registers. For example, to allow reading and writing of registers within an ASIC, it is known to directly memory-map the ASIC registers into the address space of the microprocessor. However, this may lead to a requirement for a large number of address pins on the ASIC if there are a large number of internal locations.

This requirement also extends to external memory of the ASIC in many instances as there is often a requirement for the microprocessor to access this memory through the ASIC's microprocessor interface. Again, direct memory-mapping can lead to the requirement for a large number of pins on the ASIC.

A problem with these arrangements is that the performance of the dedicated device is linked in a very close manner to that of the processor. This takes away from independence of the ASIC and may lead, for example, to the processor writing incorrect values to the ASIC. For example, if a processor failure results in erroneous writes to the ASIC, there may be severe disruption of operation of the ASIC.

It is therefore an object of the invention to provide for memory addressing without the requirement for a large number of address pins on a dedicated device.

Another object is to provide an interface which is common to a number of different dedicated devices, and to provide a more common accessing method. 1NT CL IE 980710 -2A still further object is to improve independence of dedicated circuits so that they are more tolerant of processor faults.

Another object is to allow handling of larger internal and external address space in a simple and flexible manner.

According to the invention, there is provided a circuit device comprising:access registers connected to address and data ports; and a controller comprising means for performing reads and writes to actual memoryusing addresses and data written to access registers.

In one embodiment, the controller comprises means for performing a write operation by:reading from an access register the address of an actual memory location; reading from an access register the data to be written; and writing the data to the addressed actual memory location.

In another embodiment, the controller comprises means for performing a read operation by:reading from an access register the address of an actual memory location; reading the data in the actual memory location; and writing the data to an access register for subsequent reading by the requesting device.

IE 980710 -3 * Preferably, the controller comprises means for reading an actual memory address from a plurality of access registers if the address is wider than the address port.

In one embodiment, the processor interface comprises a plurality of controllers, each connected to interface between the access registers and an associated actual memory.

In another embodiment, a controller is connected to interface between the access registers and memory external to the circuit device.

In a further embodiment, a controller is connected to interface between the access registers and internal registers.

Preferably, the controller comprises means for automatically incrementing actual memory addresses for efficient access to contiguous blocks.

In one embodiment, the controller comprises means for disabling actual memory' writes until an unlock value is written to an access lock register.

In one embodiment, the circuit device is an ASIC.

In one embodiment, the ASIC is an ATM cell processing ASIC.

According to another aspect, the invention provides a method of performing a write operation to a memory associated with a circuit device, the method comprising the steps of:writing the address of the memory location to an access register of the circuit device: and writing the desired data value to an access register.

IE 980710 -4According to a further aspect, the invention provides a method of performing a read operation from a memory- associated with a circuit device, the method comprising the steps oftwriting the address of the memory location to an access register of the circuit device; and I reading back a fetched data value from an access register.

The invention will be more clearly understood from the following description of some embodiments thereof given by way of example only with reference to Fig. I which is a schematic representation of an ASIC circuit device microprocessor interface of the invention.

The invention provides access registers in a dedicated circuit such as an ASIC’ or FPGA device. Reads and writes are performed by an external processor via the access registers to a set of a larger number of “actual” locations. Reading an actual memory location requires two steps as follows:1. writing the address of the actual location into the access registers, and 2. reading back the access register which will contain the fetched read value from the previously specified address.

A write operation requires two steps as follows:1. writing the address of the actual location into the access registers, 2. writing the desired data value to the appropriate access register (for subsequent transfer to the real location). *«= «80710 -5Referring to Fig. 1, a microprocessor interface 1 of an ASIC is illustrated. The interface 1 comprises a UPI 2 which interfaces between the external ports and internal access registers 3. The external ports include a 5-bit address port, an 8-bit data port, and two control ports. The access registers 3 include address registers, read data registers, a lock register, and auto-increment logic.

The access registers 3 are connected to a RAM port controller 4, and an internal register access controller 6. These controllers interface between the access registers 3 and the relevant memory or registers. It should be noted that these are both internal and external of the ASIC.

In this embodiment, the 5-bit address port is used to address a particular access register. The actual address is written via the 8-bit data port. If the actual address is more than 8 bits, more than one access register may be used. For example, if the actual memory is up to 64K in size addressed by 16 bits, the first write is the upper address part and the second write is the lower address part.

IE 980710 -6In more detail, the following is the set of access registers 3.

Address(hex) Name Description 00 SummarySlatus Top level status 01 AccessJ.ock Protects configuration 02 Reg_Addr_U Target address upper byte 03 , Reg_Addr_L i Target address lower byte 04 Reg_Data Data to be read/written 05—>0F not used 10 SRAM_Addr2 SRAM address upper 4 bits ll SRAMAddrl SRAM addressbytefl] 12 SRAMAddrO SRAM address bytefO] 13 SRAM_Status SRAM access status 14 SRAM_Data3 SRAM data byie[3J 15 SRAM_Data2 SRAM data b\te|2] 16 SRAM_Datal SRAM data hytefl ] 17 SRAMDataO SRAM data byteiO] 18—»1F not used This set supports four main features:5 l. Summary_Status register which allows important information to be read out directly (i.e. with only a single access). 2. AccessJLock register which allows the device to be write-protected. 3. Registers to allow access to 8-bit wider internal locations within a 16-bit internal byte-address space. 4. Registers to allow access to SRAM connected externally to the ASIC, with a 32-bit data word and 20-bit word address space.

IE 980710 -7The access registers are the locations that are directly visible in the top-level address space. Some of these registers are not simple read/write registers. Some locations (and bits within locations) are Read-Only (typically status bits) and other bits/locations are Write Only i.e. they are not real registers but are targets used to initiate some action (e.g. a write to SRAM). Some registers are read/write in the normal sense (i.e. it is possible to read back a value just written) whilst others are bi-directional where they can be used as targets for both read and write operations but what is read is not the most recently written value.

Accessing an internal register is accomplished by setting up the address of the register in access registers Reg_Addr_L and Reg_Addr_L and then either writing the required new value to access register Reg Data (causing this value to be subsequently transferred to the actual internal register) or reading the value of the internal register from Reg Data (where it will have been copied from the internal register by the act of setting up the address).

To allow' more efficient access to contiguous blocks of internal registers and external SRAM, an address auto-increment feature is implemented. This feature causes an automatic post-increment of the register address or SRAM Address following an access to either. This means that to access a contiguous series of registers or SRAM locations it is only necessary to set up the address of the starting address.

To help protect against accidental corruption of the internal configuration space and the external SRAM by a failed microprocessor (or software), an Aeeess_Lock register is provided. Writes to internal registers of SRAM will only succeed if the Aceessl.oek register has previously been written with the UNLOCK value (0xA5). During normal operation, once configuration is complete, the ASIC should be kept locked except for a configuration change. This will minimize the lime during which the .A.SIC is potentially sensitive to a faulty processor/software.

IE 980710 -8The following are examples of how some accesses are performed: Reading various internal status registers: /* partial C for accessing internal status registers */ //define reg_addr_u 0x02 //define reg_addr_l 0x03 //define reg_data 0x04 /* read status registers at addresses 0 -> 7 */ write_access_reg (reg_addr_u,0x00): /* set upper bit O */ write_access_reg (reg_addr_l ,0x00); /* set lower byte77 0 *·' for (i=0; i<7; i++) status_array[i] = read_access_reg(reg_data); /* do read and take advantage of auto15 increment */ /* now read status at addresses Ox l a and 0x7c */ wTite_access_reg(reg_addr_l,Oxla); /* set lower byle=0xla (knowing that upper bit still = 0) */ stat_a = read_access_reg(reg_data); write_access_reg(ref_addr_l,0x7c; /* set lower byte=0\7c (knowing that upper bit still = 0) */ statb = readaccessreg(regdata); Writing various configuration registers: /* partial C for setting configuration registers */ /* initialize registers at addresses Ox 12 - Ox 15 */ /* assumes that we have previously unlocked the Aceess Loek reg */ IE 980710 -9write_access_reg(reg_addr_u,0x00); /* set upper bit=0 */ write_access_reg(reg_addr_l,0xl2); /* set lower byte= 12 */ write_access_reg(reg_data,0x04); /* w rite 0x04 to I Oxi 7 * I write_access_reg(reg_data,0.x05); /* write 0x05 to Ox 13 (take advantage of auto- increment) */ write_access_reg(reg_data,QxO6); /* write 0x06 to Ox 14 (take advantage of auto- I increment) */ write_access_reg(reg_data,0x07); /* write 0x07 to Ox 15 (take advantage of auto- increment) */ /* set lower 4 bits of reg at address 0x20 (leave upper 4 unchanged) */ write_access_reg(reg_addr_l ,0x20); /* set lower byte=0.x20 (knowing that upper bit still = 0) */ orig_val = read_access_reg(ref_data); /* get original value */' write_access_reg(reg_data); /* set lower byte+0x20 again (because of auto-increment) */ write_access_ref(reg_data, orig_val&0xf3); /* sets lower 4 bits to '3' */ It will be appreciated that the invention allows a dedicated device such as an ASIC or an FPGA to require much fewer pins for processor interfacing. It also achieves more consistency in access methods to registers and memory, both internal and external. Another advantage is that it decouples the timing of the external and internal interfaces.

The invention is not limited to the embodiments described, but may be varied in construction and detail within the scope of the claims.

Claims (3)

1. A circuit device comprising:access registers connected to address and data ports; and a controller comprising means for performing reads and writes to actual memory using addresses and data written to access registers.

2. A circuit device as claimed in claim 1, wherein the controller comprises means for performing a write operation by:reading from an access register the address of an actual memory location; reading from an access register the data to be written; and writing the data to the addressed actual memory location, and wherein the controller comprises means for performing a read operation by: reading from an access register the address of an actual memory location; reading the data in the actual memory location: and writing the data to an access register for subsequent reading by the requesting device.

3. A circuit device as claimed in claims 1 or 2. wherein the controller comprises means for reading an actual memory address from a plurality of access registers if the address is wider than the address port, and wherein the processor interface comprises a plurality of controllers, each connected to interface between (he 't 980710 - I I access registers and an associated actual memory, and wherein a controller is connected to interface between the access registers and memory external to the circuit device, and wherein a controller is connected to interface between the access registers and internal registers, and wherein the controller comprises means for automatically incrementing actual memory addresses for efficient access to contiguous blocks, and wherein the controller comprises means for disabling actual memory writes until an unlock value is written to an access lock register, and wherein the circuit device is an ASIC, and wherein the ASIC is an ATM cell processing ASIC. A circuit device substantially as described with reference to the drawings. A method of performing a write operation substantially as described with reference to the drawings.