IES990134A2 - A buffer circuit for data signals - Google Patents

Abstract

A buffer circuit (1) for buffering digital data signals between an input terminal (2) and an output terminal (3), and for only relaying data signals which remain on the input (2) for at least a predetermined duration of approximately six milliseconds through a communicating circuit (4) to the output terminal (3). The input terminal (2) goes high on power up, and input signals are inverted by an inverter (U1A) and applied to a first integrating RC circuit (5) comprising a resistor (R4) and a capacitor (C2). The first RC circuit (5) holds a node (6) of the communicating circuit (4) through inverters (U1B) and (U1C) at a constant voltage for a first predetermined time until the first RC circuit (5) has charged up, at which stage the voltage on the node (6) floats, thereby enabling the communicating circuit (4). A second RC circuit (9) comprising a resistor (R5) and a capacitor (C3) holds an output pin (6) of the inverter (U1C) high after the first RC circuit (5) has discharged for permitting the voltage on the node (6) to float for a second predetermined time period, thereby enabling the communicating circuit (4) for the second predetermined time period after the signal has disappeared from the input (2). <Figure 1>

Description

The present invention relates to a buffer circuit and in particular, to a buffer circuit for buffering data signals and for relaying only data signals of at least a predetermined duration.

The radio frequency environment through which radio frequency signals pass has become noisy with many spurious interference signals and emissions being encountered. Radio controlled apparatus can be inadvertently switched by such spurious signals and emissions. This causes significant problems in the case of electronic control apparatus which in order to minimise power consumption operates in a sleep mode until it is activated by the reception of a valid type radio signal. On reception of such a valid type signal the electronic control apparatus goes into an awake mode for carrying out further analysis of the signal. In many cases, spurious radio frequency emissions may appear on a preliminary examination to the electronic Control apparatus to be valid type signals, thus putting the apparatus into an awake mode. The frequent occurrence of such spurious emissions can lead to excessively high power consumption by such apparatus. Such spurious signals and emissions can have relatively serious adverse consequences in the case of IE 990134 electronic control apparatus of keyless entry systems for motor vehicles. Such keyless entry systems, in general, are activated by a remotely transmitted radio data signal from a keyfob transmitter. The electronic control apparatus of the system remains in a sleep mode until a valid type signal is received, at which stage the electronic control apparatus goes into an awake mode for carrying out further analysis of the received signal. Accordingly, if the vehicle is parked in a radio frequency noisy environment, the electronic control apparatus of the system may be switched to the awake mode many times due to spurious emissions, which can result in relatively rapid draining of the vehicle battery. This is undesirable.

There is therefore a need for a buffer circuit which overcomes this problem.

The present invention is directed towards providing a buffer circuit for buffering data signals and for relaying only data signals of at least a predetermined duration.

According to the invention there is provided a buffer circuit for relaying only data signals of at least a predetermined duration, the buffer circuit comprising an input for receiving data signals, an output for IE 990134 outputting received data signals, a communicating means for communicating the output with the input for transferring received data signals from the input to the output, and a first integrating means for receiving data signals from the input and for integrating the received data signals with respect to time for holding the communicating means disabled for a first time period until a data signal remains on the input for at least the predetermined duration, and for enabling the communicating means for transferring a data signal from the input to the output in response to the data signal remaining on the input for the predetermined duration.

In one embodiment of the invention the first time period is equal to the predetermined duration.

In another embodiment of the invention a retaining means is provided for retaining the communicating means enabled for a second time period after a data signal has disappeared from the input.

In another embodiment of the invention the first integrating means comprises a first RC circuit connected to the input for charging thereof by a received signal, the first RC circuit co-operating with the communicating means for enabling the IE 990134 communicating means in response to the first RC circuit being charged to a level corresponding to a data signal remaining on the input for the predetermined duration. Preferably, the time constant 5 of the first RC circuit is equal to the first time period.

Preferably, a discharging means is provided for discharging the first RC circuit when a data signal has disappeared from the input for disabling the communicating means.

In another embodiment of the invention the retaining means comprises a second integrating means for integrating a signal with respect to time received from the first integrating means after the data signal has disappeared from the input, the second integrating means cooperating with the communicating means for holding the communicating means enabled for the second time period.

Preferably, the second integrating means comprises a second RC circuit connected to the output of the first integrating means for charging thereof by a signal received from the first integrating means after the data signal has disappeared from the input, the second RC circuit co-operating with the communicating means IE 990134 for holding the communicating means enabled until the second RC circuit has charged to a level corresponding to the second time period. Preferably, the time constant of the second RC circuit is equal to the second time period.

In one embodiment of the invention the first and second integrating means co-operate with each other for holding a node in the communicating means at a constant voltage for disabling the communicating means, and for allowing the voltage on the node of the communicating means to follow the voltage on the input for enabling the communicating means.

In one embodiment of the invention the buffer circuit Is adapted for receiving digitised signals.

Additionally, the invention provides a radio receiver comprising the buffer circuit according to the invention.

Further, the invention provides an electronic control apparatus for a remote keyless entry system of a motor vehicle comprising the buffer circuit according to the invention for buffering signals received from a radio receiver of the electronic control apparatus or associated therewith.

IE 990134 The invention will be more clearly understood from the following description of some embodiments thereof which are given by way of example only with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram of a buffer circuit according to the invention, Figs. 2(a) to (c) illustrate graphically the operation of the buffer circuit of Fig. 1, and Fig. 3 illustrates a circuit diagram of a buffer circuit according to another embodiment of the invention.

Referring to the drawings, and initially to Figs. 1 and 2 thereof, there is illustrated a buffer circuit according to the invention which is indicated generally by the reference numeral 1 for buffering radio data signals between an input terminal 2 and an output terminal 3, and for only relaying data signals to the output terminal 3 which remain on the input 2 for at least a predetermined duration, which in this embodiment of the invention is a first time period of 6 milliseconds approximately. The buffer circuit 1 is particularly suitable for receiving digital data signals from a radio receiver of an electronic control IE 990134 unit of a remote keyless entry system of a motor vehicle, neither of which are shown. Such data signals are of the type which are transmitted by a keyfob radio transmitter. Each such data signal, in general, comprises a sequence of identical data telegrams, and each data telegram comprises a preamble which is common to a number of electronic control units followed by a specific code which is specific to one electronic control unit only. In this particular embodiment of the invention the buffer circuit 1 is suitable for data signals each of which comprises five data telegrams of approximately 64 milliseconds duration with a time delay of 2 milliseconds approximately between the transmission of each data telegram, the duration of each data signal being approximately 330 milliseconds. Typically, a keyfob transmitter for transmitting such a data signal if continuously activated transmits a series of data signals each of approximately 330 milliseconds duration with a time delay of approximately 66 milliseconds between adjacent data signals.

The input terminal 2 which goes high on power up receives radio data signals from the radio receiver (not shown) which have been digitised prior to being applied to the input 2. A communicating means comprising a communicating circuit 4, when enabled IE 990134 relays data signals which have remained on the input 2 for at least the first time period to the output terminal 3. The communicating circuit 4 comprises a resistor Rl, first and second inverters U1D and U1E, a resistor R7, a field effect transistor Q1 and a resistor R8.

Data signals received on the input 2 are fed through a resistor R2 and a third inverter U1A to a first Integrating means, namely, a first RC circuit 5 comprising a resistor R4 and a capacitor C2 for integrating the received data signals with respect to time. The first RC circuit 5 holds the communicating circuit 4 disabled for the first time period after a signal appears on the input 2 by holding a node 6 of the communicating circuit 4 at a constant voltage through fourth and fifth inverters U1B and UIC. The time constant of the first RC circuit 5 is equal to the first time period and thus holds the communicating Circuit 4 disabled until a data signal remains on the input 2 for at least the predetermined duration. On the data signal remaining on the input 2 for the first time period, the first RC circuit 5 is charged to a level sufficient to switch the fourth inverter U1B for in turn switching the fifth inverter UIC for permitting the voltage on the node 6 to float, and thus to follow the voltage on the input 2 for enabling IE 990134 the communicating circuit 4.

Since the input 2 goes high on power up the output pin 2 of the third inverter U1A remains low until a data signal appears on the input 2 which thus causes the first RC circuit 5 to charge. For so long as the output pin 2 of the third inverter U1A remains low the input pin 3 of the fourth inverter U1B also remains low, and thus the output and input pins 4 and 5 of the fourth and fifth inverters U1B and UlC, respectively, remain high. This thus holds the output pin 6 of the fifth inverter UlC low. A low on the pin 6 of the fifth inverter UlC pulls the node 6 of the communicating circuit 4 low through a diode D5, thereby holding the voltage at the node 6 of the communicating circuit 4 low and constant irrespective of the signal on the input 2 so that the communicating circuit 4 is disabled.

On a data signal appearing on the input 2 the output pin 2 of the third inverter U1A goes high, thus causing the first RC circuit 5 to charge. After the signal has remained on the input 2 for the first time period the first RC circuit 5 will have charged to a level sufficient to switch the fourth inverter U1B thus pulling the output pin 4 of the fourth inverter U1B low, and in turn pulling the input pin 5 of the IE 990134 fifth inverter U1C also low. This thus causes the output pin 6 of the fifth inverter U1C to go high, which thus permits the node 6 in the communicating circuit 4 to follow the voltage on the input 2, thereby enabling the communicating circuit 4. The communicating circuit 4 remains enabled until the output pin 6 of the fifth inverter U1C is again pulled low as a result of the signal disappearing from the input 2, and in turn the first RC circuit 5 discharging through a discharge means, which comprises a resistor R3 and a diode D3.

A retaining means for retaining the output pin 6 of the fifth inverter U1C high for a second time period after the signal has disappeared from the input 2 comprises a second integrating means, namely, a second RC circuit 9. The second RC circuit 9 comprises a resistor R5 and a capacitor C3, and integrates the high signal on the output pin 4 of the fourth inverter U1B with respect to time when the output pin 4 goes high as a result of the signal disappearing from the input 2. The time constant of the second RC circuit 9 is equal to the second time period, and thus is such as to prevent the fifth inverter U1C switching low for the second time period for retaining the communicating circuit 4 enabled for the second time period. Thus during the second time period should the data signal IE 990134 reappear on the input 2 it is transferred to the output 3. A resistor R6 and a diode D4 discharge the second RC circuit 9 on the output pin 4 of the fourth inverter U1B going low as a result of the first RC circuit 5 again charging to a level sufficient to switch the fourth inverter U1B. The time constant of the second RC circuit 9 is selected to be of length just greater than the length of one data telegram plus the time delay between adjacent data signals, which in this embodiment of the invention is 150 milliseconds, which is just greater than 64 milliseconds plus 66 milliseconds. In this way should a complete data telegram of a data signal fail to be relayed from the input 2 to the output 3, the first complete data telegram of the next data signal is relayed to the output 3 during the second time period.

On the communicating circuit 4 being enabled, the data signal appearing on the input 2 switches the field effect transistor Q1 through the first and second inverters U1D and U1E so that a corresponding signal appears on the output 3.

In this embodiment of the invention the diodes D2, D3, D4 and D5 are Schottky barrier diodes, and the first to the fifth inverters U1A to U1E are provided by a Schmitt inverter chip. The resistors R4 and R3 are IE 990134 chosen so that the signal appearing on the input 2 and inverted through the third inverter U1A can charge the first RC circuit 5 in the first time period, while at the same time allowing the first RC circuit 5 to discharge in a reasonable time period after the signal on the input 2 has disappeared. The resistors R5 and R6 are chosen to allow the second RC circuit 9 to charge in the second time period, and to facilitate rapid discharge of the second RC circuit on the output pin 4 of the fourth inverter U1B going low.

Referring now to Figs. 2(a) to 2(c), the first and second time periods will now be described graphically. Fig. 2(a) illustrates graphically the presence of a data signal on the input 2. As can be seen the data signal begins to appear on the input 2 at time tx, and disappears at time t3. Fig. 2(b) illustrates a timing circuit of the enabling of the communicating circuit 4, and specifically illustrates the voltage on the output pin of the fifth inverter U1C. As can be seen at time t3 the voltage on the output pin 6 of the fifth inverter U1C is low. After the first time period of 6 milliseconds the first RC circuit 5 has charged to a level sufficient for switching the fourth inverter UlB, and thus the output pin 6 of the fifth inverter UlC goes high. The output pin 6 of the fifth inverter U1C remains high up to time t3 at which stage the data IE 990134 signal disappears from the input 2. However, the second RC circuit 9 holds the output pin 6 of the fifth inverter U1C high for the second time period of 150 milliseconds from time t3 to time t<. Fig. 2(c) which illustrates data signals on the output 3 illustrates that the data signals appearing on the input 2 between time t2 and time t3 are relayed to the output 3. Should data signals have appeared on the input 2 between time t3 and the time t4, these would also have been relayed to the output 3.

In use, on power up and with no data signal appearing on the input 2 the node 6 of the communicating circuit 4 is held at a constant voltage by the output pin 6 of the fifth inverter UlC being low, and thereby the communicating circuit 4 is disabled. On a data signal appearing on the input 2 the voltage on the node 6 continues to be held constant by the output pin 6 of the fifth Inverter UlC remaining low until the data signal has remained on the input 2 for the first time period, at which stage the first RC circuit 5 will have charged to a level sufficient to switch the fourth inverter U1B for pulling the output pin 4 of the fourth inverter U1B low. This in turn puts a high on the output pin 6 of the fifth inverter UlC, thereby permitting the voltage on the node 6 to float, and thus follow the voltage on the input 2. The IE 990134 communicating circuit 5 is thus enabled for facilitating transfer of the data signal on the input 2 to the output 3. On the signal disappearing from the input 2 the voltage on the node 6 remains floating due to the fact that the output pin 5 of the fifth inverter U1C remains high until the second RC circuit 9 has charged to a sufficient level for switching the fifth inverter U1C, and thus pulling the output pin 6 low. On the output pin 6 of the fifth inverter U1C being pulled low the communicating circuit 4 is again disabled.

Referring now to Fig. 3 there is illustrated a buffer circuit according to another embodiment of the invention indicated generally by the reference numeral . The buffer circuit 10 is substantially similar to the buffer circuit 1 and similar components are identified by the same reference numerals. The buffer circuit 10 is also suitable for incorporation in an electronic control apparatus of a remote keyless entry system for a motor vehicle, and operates substantially similarly as the buffer circuit 1 with the exception that on power up the input 2 of the buffer circuit 10 goes low. Accordingly, a sixth inverter U1F receives the data signals on the input 2 and the inverted data signal is fed to the third inverter U1A. Thus, when the buffer circuit 10 is powered up with no data IE 990134 appearing on the input 2 the output pin 12 of the sixth inverter U1F is high, thus causing the output pin 2 of the third inverter U1A to remain low. The presence of data on the input 2 thus causes the output pin 2 of the third inverter U1A to go high, and thereafter operation of the buffer circuit 10 is identical to that of the buffer circuit 1.

While the first time period has been selected in this embodiment of the invention to be 6 milliseconds, the first time period may be selected to be of any desirable duration. However, in the embodiments of the invention described it has been found that by maintaining the communicating circuit disabled for a first time period of approximately 6 milliseconds, the majority of spurious signals and other noise is buffered. Additionally, it will be appreciated that the second time period may be altered to allow the relaying of more than one complete date telegram of the next data signal to be relayed to the output.

While the buffer circuits have been described for use in connection with specific data signals, it will be appreciated that the buffer circuits may be adapted for use with any type of data signals. The respective time constants of the first and second RC circuits would merely be adapted to suit the type of data IE 990134 signals which were to be relayed from the input to the output.

The invention is not limited to the embodiment hereinbefore described which may be varied in construction and detail.

Claims (6)

1. A buffer circuit for relaying only data signals of at least a predetermined duration, the buffer circuit comprising an input for receiving data signals, an output for outputting received data signals, a communicating means for communicating the output with the input for transferring received data signals from the input to the output, and a first integrating means for receiving data signals from the input and for integrating the received data signals with respect to time for holding the communicating means disabled for a first time period until a data signal remains on the input for at least the predetermined duration, and for enabling the communicating means for transferring a data signal from the input to the output in response to the data signal remaining on the input for the predetermined duration.

2. A buffer circuit as claimed in Claim 1 in which a retaining means is provided for retaining the communicating means enabled for a second time period after a data signal has disappeared from the input.

3. A buffer circuit as claimed in Claim 2 in which the retaining means comprises a second integrating means for integrating a signal with respect to time received from the first integrating means after the IE 990134 data signal has disappeared from the input, the second integrating means co-operating with the communicating means for holding the communicating means enabled for the second time period.

4. 5 4. A buffer circuit as claimed in Claim 3 in which the first and second integrating means co-operate with each other for holding a node in the communicating means at a constant voltage for disabling the communicating means, and for allowing the voltage on 5. 10 the node of the communicating means to follow the voltage on the input for enabling the communicating means.

5. A buffer circuit for relaying only data signals of at least a predetermined duration, the buffer circuit

6. 15 being substantially as described herein with reference to and as illustrated in the accompanying drawings.