IL120514A - Electronic interconnect structure and method for manufacturing it - Google Patents

Electronic interconnect structure and method for manufacturing it

Info

Publication number
IL120514A
IL120514A IL12051497A IL12051497A IL120514A IL 120514 A IL120514 A IL 120514A IL 12051497 A IL12051497 A IL 12051497A IL 12051497 A IL12051497 A IL 12051497A IL 120514 A IL120514 A IL 120514A
Authority
IL
Israel
Prior art keywords
manufacturing
interconnect structure
electronic interconnect
electronic
interconnect
Prior art date
Application number
IL12051497A
Other languages
English (en)
Other versions
IL120514A0 (en
Original Assignee
P C B Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by P C B Ltd filed Critical P C B Ltd
Priority to IL12051497A priority Critical patent/IL120514A/xx
Priority to US08/835,514 priority patent/US5946600A/en
Publication of IL120514A0 publication Critical patent/IL120514A0/xx
Priority to JP11987498A priority patent/JP3359865B2/ja
Priority to DE69821399T priority patent/DE69821399T2/de
Priority to EP98302252A priority patent/EP0867929B1/de
Priority to DE69827851T priority patent/DE69827851T2/de
Priority to EP00127124A priority patent/EP1093163B1/de
Publication of IL120514A publication Critical patent/IL120514A/xx

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1142—Conversion of conductive material into insulating material or into dissolvable compound
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IL12051497A 1997-03-25 1997-03-25 Electronic interconnect structure and method for manufacturing it IL120514A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IL12051497A IL120514A (en) 1997-03-25 1997-03-25 Electronic interconnect structure and method for manufacturing it
US08/835,514 US5946600A (en) 1997-03-25 1997-04-08 Method for manufacturing an electronic structure
JP11987498A JP3359865B2 (ja) 1997-03-25 1998-03-25 エレクトロニック相互接続構造及びそれを製造するための方法
DE69821399T DE69821399T2 (de) 1997-03-25 1998-03-25 Elektronische Verdrahtungsstruktur und ihre Herstellung
EP98302252A EP0867929B1 (de) 1997-03-25 1998-03-25 Elektronische Verdrahtungsstruktur und ihre Herstellung
DE69827851T DE69827851T2 (de) 1997-03-25 1998-03-25 Elektronische Verdrahtungsstruktur
EP00127124A EP1093163B1 (de) 1997-03-25 1998-03-25 Elektronische Verdrahtungsstruktur

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IL12051497A IL120514A (en) 1997-03-25 1997-03-25 Electronic interconnect structure and method for manufacturing it
US08/835,514 US5946600A (en) 1997-03-25 1997-04-08 Method for manufacturing an electronic structure

Publications (2)

Publication Number Publication Date
IL120514A0 IL120514A0 (en) 1997-07-13
IL120514A true IL120514A (en) 2000-08-31

Family

ID=26323395

Family Applications (1)

Application Number Title Priority Date Filing Date
IL12051497A IL120514A (en) 1997-03-25 1997-03-25 Electronic interconnect structure and method for manufacturing it

Country Status (4)

Country Link
US (1) US5946600A (de)
EP (1) EP0867929B1 (de)
JP (1) JP3359865B2 (de)
IL (1) IL120514A (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262478B1 (en) * 1997-04-08 2001-07-17 Amitec-Advanced Multilayer Interconnect Technologies Ltd. Electronic interconnect structure and method for manufacturing it
IL120866A0 (en) * 1997-05-20 1997-09-30 Micro Components Systems Ltd Process for producing an aluminum substrate
US6261934B1 (en) * 1998-03-31 2001-07-17 Texas Instruments Incorporated Dry etch process for small-geometry metal gates over thin gate dielectric
IL127256A (en) 1998-11-25 2002-09-12 Micro Components Ltd Device for electronic packaging, a process for manufacturing thereof, and a pin jig fixture for use in the process
US6291339B1 (en) * 1999-01-04 2001-09-18 Advanced Micro Devices, Inc. Bilayer interlayer dielectric having a substantially uniform composite interlayer dielectric constant over pattern features of varying density and method of making the same
IL128200A (en) * 1999-01-24 2003-11-23 Amitec Advanced Multilayer Int Chip carrier substrate
JP4428832B2 (ja) * 1999-08-27 2010-03-10 富士通株式会社 金属配線構造、半導体装置及び半導体装置の製造方法
US6387818B1 (en) * 2000-07-21 2002-05-14 Advanced Micro Devices, Inc. Method of porous dielectric formation with anodic template
US6975189B1 (en) * 2000-11-02 2005-12-13 Telasic Communications, Inc. On-chip multilayer metal shielded transmission line
TW561805B (en) * 2001-05-16 2003-11-11 Unimicron Technology Corp Fabrication method of micro-via
US20040007376A1 (en) * 2002-07-09 2004-01-15 Eric Urdahl Integrated thermal vias
JP4035066B2 (ja) * 2003-02-04 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2004349593A (ja) * 2003-05-26 2004-12-09 Sanyo Electric Co Ltd 半導体装置及びその製造方法
ITTO20030409A1 (it) * 2003-06-03 2004-12-04 Fiat Ricerche Biosensore ottico.
US7164197B2 (en) * 2003-06-19 2007-01-16 3M Innovative Properties Company Dielectric composite material
US7265448B2 (en) 2004-01-26 2007-09-04 Marvell World Trade Ltd. Interconnect structure for power transistors
US7851872B2 (en) 2003-10-22 2010-12-14 Marvell World Trade Ltd. Efficient transistor structure
US7960833B2 (en) 2003-10-22 2011-06-14 Marvell World Trade Ltd. Integrated circuits and interconnect structure for integrated circuits
US7521358B2 (en) * 2006-12-26 2009-04-21 Lam Research Corporation Process integration scheme to lower overall dielectric constant in BEoL interconnect structures
US8551682B2 (en) * 2007-08-15 2013-10-08 Dynaloy, Llc Metal conservation with stripper solutions containing resorcinol
US7960835B2 (en) * 2009-05-04 2011-06-14 Macronix International Co., Ltd. Fabrication of metal film stacks having improved bottom critical dimension
KR101289186B1 (ko) * 2011-04-15 2013-07-26 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US9144150B2 (en) 2012-04-20 2015-09-22 Xilinx, Inc. Conductor structure with integrated via element
TWI559465B (zh) * 2015-08-14 2016-11-21 恆勁科技股份有限公司 封裝基板及其製作方法
US10134580B1 (en) * 2017-08-15 2018-11-20 Globalfoundries Inc. Metallization levels and methods of making thereof
TWI642333B (zh) 2017-10-25 2018-11-21 欣興電子股份有限公司 電路板及其製造方法
TWI642334B (zh) * 2017-10-25 2018-11-21 欣興電子股份有限公司 電路板及其製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3210214A (en) * 1962-11-29 1965-10-05 Sylvania Electric Prod Electrical conductive patterns
FR2288392A1 (fr) * 1974-10-18 1976-05-14 Radiotechnique Compelec Procede de realisation de dispositifs semiconducteurs
JPS5544765A (en) * 1978-09-25 1980-03-29 Nec Kyushu Ltd Manufacture of semiconductor
US4531144A (en) * 1982-05-14 1985-07-23 Burroughs Corporation Aluminum-refractory metal interconnect with anodized periphery
US5580825A (en) * 1993-09-20 1996-12-03 International Technology Exchange Corp. Process for making multilevel interconnections of electronic components
IL110431A (en) * 1994-07-25 2001-08-08 Microcomponents And Systems Lt Method of manufacturing a composite structure for use in electronic device and structure manufactured by said method
US5705428A (en) * 1995-08-03 1998-01-06 Chartered Semiconductor Manufacturing Pte, Ltd. Method for preventing titanium lifting during and after metal etching
US5731047A (en) * 1996-11-08 1998-03-24 W.L. Gore & Associates, Inc. Multiple frequency processing to improve electrical resistivity of blind micro-vias

Also Published As

Publication number Publication date
JPH11145625A (ja) 1999-05-28
US5946600A (en) 1999-08-31
EP0867929A3 (de) 1999-04-14
JP3359865B2 (ja) 2002-12-24
EP0867929B1 (de) 2004-02-04
IL120514A0 (en) 1997-07-13
EP0867929A2 (de) 1998-09-30

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