IN2013CH04449A - - Google Patents

Info

Publication number
IN2013CH04449A
IN2013CH04449A IN4449CH2013A IN2013CH04449A IN 2013CH04449 A IN2013CH04449 A IN 2013CH04449A IN 4449CH2013 A IN4449CH2013 A IN 4449CH2013A IN 2013CH04449 A IN2013CH04449 A IN 2013CH04449A
Authority
IN
India
Prior art keywords
data block
core
stored
ready state
stored data
Prior art date
Application number
Inventor
Vajapeyam Sriram
Original Assignee
Empire Technology Dev Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Empire Technology Dev Llc filed Critical Empire Technology Dev Llc
Priority to IN4449CH2013 priority Critical patent/IN2013CH04449A/en
Priority to US14/383,895 priority patent/US9864709B2/en
Publication of IN2013CH04449A publication Critical patent/IN2013CH04449A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/622—State-only directory, i.e. not recording identity of sharing or owning nodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Techniques described herein are generally related to data transfer in multi-core processor devices. A first core of the multi-core processor device may be configured to receive a request for a data block. The requested data block may be stored in a private cache of the first core. The data block in the private cache may be evaluated by a coherence module of the first core to determine when the stored data block is in a ready state. A program slice associated with the data block may be identified by the coherence module when the stored data block is determined to be in an unavailable state and the identified program slice may be executed by the first core effective to update the stored data block from the unavailable state to the ready state. The data block may be sent to an interconnect network in response to the received request when the stored data block is determined to be in the ready state.
IN4449CH2013 2013-09-30 2013-09-30 IN2013CH04449A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IN4449CH2013 IN2013CH04449A (en) 2013-09-30 2013-09-30
US14/383,895 US9864709B2 (en) 2013-09-30 2013-11-21 Data transfer in a multi-core processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN4449CH2013 IN2013CH04449A (en) 2013-09-30 2013-09-30

Publications (1)

Publication Number Publication Date
IN2013CH04449A true IN2013CH04449A (en) 2015-04-03

Family

ID=54209872

Family Applications (1)

Application Number Title Priority Date Filing Date
IN4449CH2013 IN2013CH04449A (en) 2013-09-30 2013-09-30

Country Status (2)

Country Link
US (1) US9864709B2 (en)
IN (1) IN2013CH04449A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
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CN115114192A (en) * 2021-03-23 2022-09-27 北京灵汐科技有限公司 Memory interface, functional core, many-core system and storage data access method

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CN116594758B (en) * 2023-07-18 2023-09-26 山东三未信安信息科技有限公司 Password module call optimization system and optimization method

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Publication number Priority date Publication date Assignee Title
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Also Published As

Publication number Publication date
US20150286597A1 (en) 2015-10-08
US9864709B2 (en) 2018-01-09

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