IN2014CH00859A - - Google Patents
Info
- Publication number
- IN2014CH00859A IN2014CH00859A IN859CH2014A IN2014CH00859A IN 2014CH00859 A IN2014CH00859 A IN 2014CH00859A IN 859CH2014 A IN859CH2014 A IN 859CH2014A IN 2014CH00859 A IN2014CH00859 A IN 2014CH00859A
- Authority
- IN
- India
- Prior art keywords
- instruction
- instructions
- test
- operand
- branch
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/52—Binary to binary
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
- G06F9/45516—Runtime code conversion or optimisation
- G06F9/4552—Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/842,754 US9886277B2 (en) | 2013-03-15 | 2013-03-15 | Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IN2014CH00859A true IN2014CH00859A (de) | 2015-04-24 |
Family
ID=50440386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IN859CH2014 IN2014CH00859A (de) | 2013-03-15 | 2014-02-21 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9886277B2 (de) |
| JP (2) | JP2014194755A (de) |
| KR (1) | KR101712864B1 (de) |
| CN (1) | CN104049945B (de) |
| DE (1) | DE102014003795A1 (de) |
| GB (1) | GB2512726B (de) |
| IN (1) | IN2014CH00859A (de) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10310860B2 (en) | 2016-07-29 | 2019-06-04 | International Business Machines Corporation | Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor |
Families Citing this family (49)
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|---|---|---|---|---|
| GB2480285A (en) * | 2010-05-11 | 2011-11-16 | Advanced Risc Mach Ltd | Conditional compare instruction which sets a condition code when it is not executed |
| US9513906B2 (en) | 2013-01-23 | 2016-12-06 | International Business Machines Corporation | Vector checksum instruction |
| US9823924B2 (en) | 2013-01-23 | 2017-11-21 | International Business Machines Corporation | Vector element rotate and insert under mask instruction |
| US9672037B2 (en) * | 2013-01-23 | 2017-06-06 | Apple Inc. | Arithmetic branch fusion |
| US9804840B2 (en) | 2013-01-23 | 2017-10-31 | International Business Machines Corporation | Vector Galois Field Multiply Sum and Accumulate instruction |
| US9778932B2 (en) | 2013-01-23 | 2017-10-03 | International Business Machines Corporation | Vector generate mask instruction |
| US9471308B2 (en) | 2013-01-23 | 2016-10-18 | International Business Machines Corporation | Vector floating point test data class immediate instruction |
| US9715385B2 (en) | 2013-01-23 | 2017-07-25 | International Business Machines Corporation | Vector exception code |
| US9483266B2 (en) * | 2013-03-15 | 2016-11-01 | Intel Corporation | Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sources |
| KR20140134376A (ko) * | 2013-05-14 | 2014-11-24 | 한국전자통신연구원 | 오류감지가 가능한 프로세서 및 이를 이용한 프로세서 코어 오류 감지 방법 |
| US20160179542A1 (en) * | 2014-12-23 | 2016-06-23 | Patrick P. Lai | Instruction and logic to perform a fused single cycle increment-compare-jump |
| US10409599B2 (en) | 2015-06-26 | 2019-09-10 | Microsoft Technology Licensing, Llc | Decoding information about a group of instructions including a size of the group of instructions |
| US10169044B2 (en) | 2015-06-26 | 2019-01-01 | Microsoft Technology Licensing, Llc | Processing an encoding format field to interpret header information regarding a group of instructions |
| US11755484B2 (en) | 2015-06-26 | 2023-09-12 | Microsoft Technology Licensing, Llc | Instruction block allocation |
| US9946548B2 (en) | 2015-06-26 | 2018-04-17 | Microsoft Technology Licensing, Llc | Age-based management of instruction blocks in a processor instruction window |
| US9952867B2 (en) | 2015-06-26 | 2018-04-24 | Microsoft Technology Licensing, Llc | Mapping instruction blocks based on block size |
| US10346168B2 (en) | 2015-06-26 | 2019-07-09 | Microsoft Technology Licensing, Llc | Decoupled processor instruction window and operand buffer |
| US10191747B2 (en) | 2015-06-26 | 2019-01-29 | Microsoft Technology Licensing, Llc | Locking operand values for groups of instructions executed atomically |
| US9940136B2 (en) | 2015-06-26 | 2018-04-10 | Microsoft Technology Licensing, Llc | Reuse of decoded instructions |
| US10409606B2 (en) | 2015-06-26 | 2019-09-10 | Microsoft Technology Licensing, Llc | Verifying branch targets |
| US10175988B2 (en) | 2015-06-26 | 2019-01-08 | Microsoft Technology Licensing, Llc | Explicit instruction scheduler state information for a processor |
| US10095519B2 (en) | 2015-09-19 | 2018-10-09 | Microsoft Technology Licensing, Llc | Instruction block address register |
| GB2543304B (en) * | 2015-10-14 | 2020-10-28 | Advanced Risc Mach Ltd | Move prefix instruction |
| US10324724B2 (en) * | 2015-12-16 | 2019-06-18 | Intel Corporation | Hardware apparatuses and methods to fuse instructions |
| US20170192788A1 (en) * | 2016-01-05 | 2017-07-06 | Intel Corporation | Binary translation support using processor instruction prefixes |
| ES2933675T3 (es) * | 2016-12-31 | 2023-02-13 | Intel Corp | Sistemas, métodos y aparatos para informática heterogénea |
| US10372452B2 (en) * | 2017-03-14 | 2019-08-06 | Samsung Electronics Co., Ltd. | Memory load to load fusing |
| GB2560892B (en) | 2017-03-23 | 2021-06-02 | Advanced Risc Mach Ltd | Graphics Processing |
| US10559056B2 (en) * | 2017-06-12 | 2020-02-11 | Arm Limited | Graphics processing |
| US10592246B2 (en) | 2017-07-12 | 2020-03-17 | International Business Machines Corporation | Low latency execution of floating-point record form instructions |
| US11150908B2 (en) * | 2017-08-18 | 2021-10-19 | International Business Machines Corporation | Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence |
| GB2569275B (en) * | 2017-10-20 | 2020-06-03 | Graphcore Ltd | Time deterministic exchange |
| CN108509202A (zh) * | 2018-03-30 | 2018-09-07 | 天津麒麟信息技术有限公司 | 基于飞腾平台火狐浏览器jit引擎的整数乘法优化方法 |
| US10534881B2 (en) * | 2018-04-10 | 2020-01-14 | Advanced Micro Devices, Inc. | Method of debugging a processor |
| US10996952B2 (en) | 2018-12-10 | 2021-05-04 | SiFive, Inc. | Macro-op fusion |
| WO2021250689A1 (en) * | 2020-06-12 | 2021-12-16 | Gulzar Singh | Novel hardware accelerator circuit for bit-level operations in a microcontroller |
| US12504958B2 (en) | 2020-09-09 | 2025-12-23 | Ascenium, Inc. | Compute element processing using control word templates |
| US12578991B2 (en) | 2020-09-09 | 2026-03-17 | Ascenium, Inc. | Parallel processing architecture with distributed register files |
| US12493554B2 (en) | 2020-09-09 | 2025-12-09 | Ascenium, Inc. | Parallel processing using hazard detection and mitigation |
| CN112214242A (zh) * | 2020-09-23 | 2021-01-12 | 上海赛昉科技有限公司 | 一种risc-v指令压缩方法、系统及计算机可读介质 |
| CN112346780B (zh) * | 2020-11-05 | 2022-11-15 | 海光信息技术股份有限公司 | 一种信息处理方法、装置和存储介质 |
| US11714649B2 (en) * | 2021-11-29 | 2023-08-01 | Shandong Lingneng Electronic Technology Co., Ltd. | RISC-V-based 3D interconnected multi-core processor architecture and working method thereof |
| US12613696B2 (en) * | 2021-12-22 | 2026-04-28 | Intel Corporation | System, apparatus and method for throttling fusion of micro-operations in a processor |
| TW202411838A (zh) * | 2022-07-12 | 2024-03-16 | 美商賽發馥股份有限公司 | 與破壞性指令融合 |
| CN115562725A (zh) * | 2022-09-22 | 2023-01-03 | 平头哥(上海)半导体技术有限公司 | 指令融合方法、处理器、计算机系统及存储介质 |
| US12487829B2 (en) | 2023-02-03 | 2025-12-02 | SiFive, Inc. | Macro-op fusion for pipelined architectures |
| CN117193861B (zh) * | 2023-11-07 | 2024-03-15 | 芯来智融半导体科技(上海)有限公司 | 指令处理方法、装置、计算机设备和存储介质 |
| US12561141B2 (en) * | 2024-04-15 | 2026-02-24 | Condor Computing Corporation | Apparatus and method for improving instruction fusion, fracture, and binary translation |
| CN118312220B (zh) * | 2024-06-11 | 2024-08-30 | 北京微核芯科技有限公司 | 指令的发送方法、装置及设备 |
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| EP0723680B1 (de) | 1993-10-12 | 1998-08-12 | Samsung Electronics Co., Ltd. | Hardware-unterstützter zählungsänderungsbefehl |
| US5596763A (en) | 1993-11-30 | 1997-01-21 | Texas Instruments Incorporated | Three input arithmetic logic unit forming mixed arithmetic and boolean combinations |
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| WO1997027536A1 (en) * | 1996-01-24 | 1997-07-31 | Sun Microsystems, Inc. | Instruction folding for a stack-based machine |
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| US20110138156A1 (en) | 2009-10-15 | 2011-06-09 | Awad Tom | Method and apparatus for evaluating a logical expression and processor making use of same |
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| US9672037B2 (en) | 2013-01-23 | 2017-06-06 | Apple Inc. | Arithmetic branch fusion |
| US9483266B2 (en) * | 2013-03-15 | 2016-11-01 | Intel Corporation | Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sources |
-
2013
- 2013-03-15 US US13/842,754 patent/US9886277B2/en not_active Expired - Fee Related
-
2014
- 2014-02-18 JP JP2014028261A patent/JP2014194755A/ja active Pending
- 2014-02-19 GB GB1402906.0A patent/GB2512726B/en active Active
- 2014-02-21 IN IN859CH2014 patent/IN2014CH00859A/en unknown
- 2014-03-12 KR KR1020140029213A patent/KR101712864B1/ko not_active Expired - Fee Related
- 2014-03-14 CN CN201410097423.XA patent/CN104049945B/zh active Active
- 2014-03-17 DE DE102014003795.9A patent/DE102014003795A1/de not_active Withdrawn
-
2015
- 2015-12-24 JP JP2015251651A patent/JP6227621B2/ja active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10310860B2 (en) | 2016-07-29 | 2019-06-04 | International Business Machines Corporation | Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101712864B1 (ko) | 2017-03-08 |
| US9886277B2 (en) | 2018-02-06 |
| GB2512726B (en) | 2016-02-10 |
| JP2014194755A (ja) | 2014-10-09 |
| CN104049945A (zh) | 2014-09-17 |
| GB201402906D0 (en) | 2014-04-02 |
| CN104049945B (zh) | 2018-11-30 |
| JP6227621B2 (ja) | 2017-11-08 |
| DE102014003795A1 (de) | 2014-09-18 |
| US20140281389A1 (en) | 2014-09-18 |
| KR20140113432A (ko) | 2014-09-24 |
| JP2016103280A (ja) | 2016-06-02 |
| GB2512726A (en) | 2014-10-08 |
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