IT1050024B - Matrice logica perfezionata - Google Patents

Matrice logica perfezionata

Info

Publication number
IT1050024B
IT1050024B IT30097/75A IT3009775A IT1050024B IT 1050024 B IT1050024 B IT 1050024B IT 30097/75 A IT30097/75 A IT 30097/75A IT 3009775 A IT3009775 A IT 3009775A IT 1050024 B IT1050024 B IT 1050024B
Authority
IT
Italy
Prior art keywords
perfected
logic matrix
logic
matrix
perfected logic
Prior art date
Application number
IT30097/75A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1050024B publication Critical patent/IT1050024B/it

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT30097/75A 1974-12-30 1975-12-09 Matrice logica perfezionata IT1050024B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/537,218 US3936812A (en) 1974-12-30 1974-12-30 Segmented parallel rail paths for input/output signals

Publications (1)

Publication Number Publication Date
IT1050024B true IT1050024B (it) 1981-03-10

Family

ID=24141726

Family Applications (1)

Application Number Title Priority Date Filing Date
IT30097/75A IT1050024B (it) 1974-12-30 1975-12-09 Matrice logica perfezionata

Country Status (6)

Country Link
US (1) US3936812A (it)
JP (1) JPS5178950A (it)
CA (1) CA1045214A (it)
DE (1) DE2556274C2 (it)
GB (1) GB1473028A (it)
IT (1) IT1050024B (it)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4029970A (en) * 1975-11-06 1977-06-14 Ibm Corporation Changeable decoder structure for a folded logic array
US4025799A (en) * 1975-11-06 1977-05-24 Ibm Corporation Decoder structure for a folded logic array
JPS5911980B2 (ja) * 1975-12-23 1984-03-19 日本電気株式会社 ランダムアクセスメモリソウチ
US4156938A (en) * 1975-12-29 1979-05-29 Mostek Corporation MOSFET Memory chip with single decoder and bi-level interconnect lines
US4040029A (en) * 1976-05-21 1977-08-02 Rca Corporation Memory system with reduced block decoding
US4032894A (en) * 1976-06-01 1977-06-28 International Business Machines Corporation Logic array with enhanced flexibility
US4063080A (en) * 1976-06-30 1977-12-13 International Business Machines Corporation Method of propagation delay testing a level sensitive array logic system
US4140967A (en) * 1977-06-24 1979-02-20 International Business Machines Corporation Merged array PLA device, circuit, fabrication method and testing technique
US4212026A (en) * 1977-06-24 1980-07-08 International Business Machines Corporation Merged array PLA device, circuit, fabrication method and testing technique
US4139907A (en) * 1977-08-31 1979-02-13 Bell Telephone Laboratories, Incorporated Integrated read only memory
US4177452A (en) * 1978-06-05 1979-12-04 International Business Machines Corporation Electrically programmable logic array
JPS558135A (en) * 1978-07-04 1980-01-21 Mamoru Tanaka Rewritable programable logic array
US4438427A (en) * 1978-07-20 1984-03-20 Fujitsu Limited Decoder and method utilizing partial and redundant decoding
JPS5843905B2 (ja) * 1979-07-31 1983-09-29 富士通株式会社 半導体集積回路の製造方法
US4357678A (en) * 1979-12-26 1982-11-02 International Business Machines Corporation Programmable sequential logic array mechanism
US4377849A (en) * 1980-12-29 1983-03-22 International Business Machines Corporation Macro assembler process for automated circuit design
JPS57124463A (en) * 1981-01-26 1982-08-03 Nec Corp Semiconductor device
JPS57211248A (en) * 1981-06-22 1982-12-25 Hitachi Ltd Semiconductor integrated circuit device
US4467439A (en) * 1981-06-30 1984-08-21 Ibm Corporation OR Product term function in the search array of a PLA
US4433331A (en) * 1981-12-14 1984-02-21 Bell Telephone Laboratories, Incorporated Programmable logic array interconnection matrix
US4506341A (en) * 1982-06-10 1985-03-19 International Business Machines Corporation Interlaced programmable logic array having shared elements
JPS609152A (ja) * 1983-06-29 1985-01-18 Fujitsu Ltd 半導体装置
USRE34363E (en) * 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4761768A (en) * 1985-03-04 1988-08-02 Lattice Semiconductor Corporation Programmable logic device
US4758746A (en) * 1985-08-12 1988-07-19 Monolithic Memories, Inc. Programmable logic array with added array of gates and added output routing flexibility
JPH0642536B2 (ja) * 1985-08-16 1994-06-01 富士通株式会社 半導体記憶装置
ATE99473T1 (de) * 1985-09-11 1994-01-15 Pilkington Micro Electronics Integrierte halbleiterschaltungen.
DE3765695D1 (de) * 1986-05-30 1990-11-29 Siemens Ag Programmierbare schaltungsanordnung.
US5367208A (en) * 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
US4880754A (en) * 1987-07-06 1989-11-14 International Business Machines Corp. Method for providing engineering changes to LSI PLAs
JPH01220712A (ja) * 1988-02-25 1989-09-04 Yamaha Corp 化粧部材の取付構造
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3033914A (en) * 1960-04-20 1962-05-08 Gen Electric Printed circuit boards
US3761902A (en) * 1971-12-30 1973-09-25 Ibm Functional memory using multi-state associative cells

Also Published As

Publication number Publication date
JPS5178950A (en) 1976-07-09
GB1473028A (en) 1977-05-11
DE2556274A1 (de) 1976-07-08
JPS5626183B2 (it) 1981-06-17
US3936812A (en) 1976-02-03
DE2556274C2 (de) 1982-08-12
CA1045214A (en) 1978-12-26

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