IT1100525B - Procedimento per fabbricare un circuito integrato comprendente strati a gradini costituiti di materiale isolante e di materiale elettrodico - Google Patents
Procedimento per fabbricare un circuito integrato comprendente strati a gradini costituiti di materiale isolante e di materiale elettrodicoInfo
- Publication number
- IT1100525B IT1100525B IT30439/78A IT3043978A IT1100525B IT 1100525 B IT1100525 B IT 1100525B IT 30439/78 A IT30439/78 A IT 30439/78A IT 3043978 A IT3043978 A IT 3043978A IT 1100525 B IT1100525 B IT 1100525B
- Authority
- IT
- Italy
- Prior art keywords
- electrodical
- procedure
- manufacturing
- integrated circuit
- circuit including
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19772754066 DE2754066A1 (de) | 1977-12-05 | 1977-12-05 | Herstellung einer integrierten schaltung mit abgestuften schichten aus isolations- und elektrodenmaterial |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| IT7830439A0 IT7830439A0 (it) | 1978-12-01 |
| IT1100525B true IT1100525B (it) | 1985-09-28 |
Family
ID=6025318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT30439/78A IT1100525B (it) | 1977-12-05 | 1978-12-01 | Procedimento per fabbricare un circuito integrato comprendente strati a gradini costituiti di materiale isolante e di materiale elettrodico |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0003733B1 (it) |
| JP (1) | JPS5491060A (it) |
| DE (2) | DE2754066A1 (it) |
| IT (1) | IT1100525B (it) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2460037A1 (fr) * | 1979-06-22 | 1981-01-16 | Thomson Csf | Procede d'auto-alignement de regions differemment dopees d'une structure de semi-conducteur |
| DE2926417A1 (de) * | 1979-06-29 | 1981-01-22 | Siemens Ag | Dynamische halbleiterspeicherzelle und verfahren zu ihrer herstellung |
| DE2947350A1 (de) * | 1979-11-23 | 1981-05-27 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von mnos-speichertransistoren mit sehr kurzer kanallaenge in silizium-gate-technologie |
| JPS56114319A (en) * | 1980-02-14 | 1981-09-08 | Fujitsu Ltd | Method for forming contact hole |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL143070B (nl) * | 1964-04-21 | 1974-08-15 | Philips Nv | Werkwijze voor het aanbrengen van naast elkaar gelegen, door een tussenruimte van elkaar gescheiden metaaldelen op een ondergrond en voorwerp, in het bijzonder halfgeleiderinrichting, vervaardigd met toepassing van deze werkwijze. |
| JPS4953776A (it) * | 1972-09-27 | 1974-05-24 | ||
| DE2723933A1 (de) * | 1975-12-04 | 1978-06-01 | Siemens Ag | Verfahren zur erzeugung definierter boeschungswinkel bei einer aetzkante |
| DE2703877C2 (de) * | 1977-01-31 | 1982-06-03 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | MIS-Transistor von kurzer Kanallänge und Verfahren zu seiner Herstellung |
-
1977
- 1977-12-05 DE DE19772754066 patent/DE2754066A1/de not_active Withdrawn
-
1978
- 1978-11-20 EP EP78101414A patent/EP0003733B1/de not_active Expired
- 1978-11-20 DE DE7878101414T patent/DE2860611D1/de not_active Expired
- 1978-12-01 IT IT30439/78A patent/IT1100525B/it active
- 1978-12-04 JP JP15049278A patent/JPS5491060A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| DE2754066A1 (de) | 1979-06-13 |
| DE2860611D1 (en) | 1981-04-30 |
| EP0003733A1 (de) | 1979-09-05 |
| EP0003733B1 (de) | 1981-04-08 |
| JPS5491060A (en) | 1979-07-19 |
| IT7830439A0 (it) | 1978-12-01 |
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