IT1101311B - J-fet,canale p,a bassa tensione di pinch-off - Google Patents
J-fet,canale p,a bassa tensione di pinch-offInfo
- Publication number
- IT1101311B IT1101311B IT30894/78A IT3089478A IT1101311B IT 1101311 B IT1101311 B IT 1101311B IT 30894/78 A IT30894/78 A IT 30894/78A IT 3089478 A IT3089478 A IT 3089478A IT 1101311 B IT1101311 B IT 1101311B
- Authority
- IT
- Italy
- Prior art keywords
- fet
- pinch
- channel
- low voltage
- voltage
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/80—FETs having rectifying junction gate electrodes
- H10D30/83—FETs having PN junction gate electrodes
- H10D30/831—Vertical FETs having PN junction gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/30—Isolation regions comprising PN junctions
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT30894/78A IT1101311B (it) | 1978-12-15 | 1978-12-15 | J-fet,canale p,a bassa tensione di pinch-off |
| FR7929738A FR2444340A1 (fr) | 1978-12-15 | 1979-12-04 | Transistor a effet de champ a jonction a canal p a basse tension de pincement |
| SE7910189A SE437200B (sv) | 1978-12-15 | 1979-12-11 | Integrerad halvledaranordning bestaende av minst en unipoler felteffekttransistor av sperrskiktstyp med en p-kanal |
| DE19792950452 DE2950452A1 (de) | 1978-12-15 | 1979-12-14 | P-kanal - j-fet mit niedriger abschnuerspannung |
| US06/103,423 US4266233A (en) | 1978-12-15 | 1979-12-14 | I-C Wafer incorporating junction-type field-effect transistor |
| JP16172579A JPS55117256A (en) | 1978-12-15 | 1979-12-14 | Integrated circuit device |
| GB7943351A GB2037078A (en) | 1978-12-15 | 1979-12-17 | P channel j-fet with low pinch-off voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT30894/78A IT1101311B (it) | 1978-12-15 | 1978-12-15 | J-fet,canale p,a bassa tensione di pinch-off |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| IT7830894A0 IT7830894A0 (it) | 1978-12-15 |
| IT1101311B true IT1101311B (it) | 1985-09-28 |
Family
ID=11232705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT30894/78A IT1101311B (it) | 1978-12-15 | 1978-12-15 | J-fet,canale p,a bassa tensione di pinch-off |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4266233A (it) |
| JP (1) | JPS55117256A (it) |
| DE (1) | DE2950452A1 (it) |
| FR (1) | FR2444340A1 (it) |
| GB (1) | GB2037078A (it) |
| IT (1) | IT1101311B (it) |
| SE (1) | SE437200B (it) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3072002D1 (en) * | 1979-11-14 | 1987-09-10 | Fujitsu Ltd | An output transistor of a ttl device with a means for discharging carriers |
| US4833095A (en) * | 1985-02-19 | 1989-05-23 | Eaton Corporation | Method for buried channel field effect transistor for microwave and millimeter frequencies utilizing ion implantation |
| US4837175A (en) * | 1983-02-15 | 1989-06-06 | Eaton Corporation | Making a buried channel FET with lateral growth over amorphous region |
| US4624004A (en) | 1985-07-15 | 1986-11-18 | Eaton Corporation | Buried channel MESFET with backside source contact |
| US4724220A (en) * | 1985-02-19 | 1988-02-09 | Eaton Corporation | Method for fabricating buried channel field-effect transistor for microwave and millimeter frequencies |
| US4935789A (en) * | 1985-02-19 | 1990-06-19 | Eaton Corporation | Buried channel FET with lateral growth over amorphous region |
| US5610079A (en) * | 1995-06-19 | 1997-03-11 | Reliance Electric Industrial Company | Self-biased moat for parasitic current suppression in integrated circuits |
| US5945699A (en) * | 1997-05-13 | 1999-08-31 | Harris Corporation | Reduce width, differentially doped vertical JFET device |
| US6710538B1 (en) * | 1998-08-26 | 2004-03-23 | Micron Technology, Inc. | Field emission display having reduced power requirements and method |
| JP4907736B2 (ja) * | 2011-02-22 | 2012-04-04 | 鹿島建設株式会社 | サンゴ礁の造成方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4181542A (en) * | 1976-10-25 | 1980-01-01 | Nippon Gakki Seizo Kabushiki Kaisha | Method of manufacturing junction field effect transistors |
| JPS5368178A (en) * | 1976-11-30 | 1978-06-17 | Handotai Kenkyu Shinkokai | Fet transistor |
| US4095252A (en) * | 1976-12-27 | 1978-06-13 | National Semiconductor Corporation | Composite jfet-bipolar transistor structure |
| US4170019A (en) * | 1977-08-05 | 1979-10-02 | General Electric Company | Semiconductor device with variable grid openings for controlling turn-off pattern |
-
1978
- 1978-12-15 IT IT30894/78A patent/IT1101311B/it active
-
1979
- 1979-12-04 FR FR7929738A patent/FR2444340A1/fr not_active Withdrawn
- 1979-12-11 SE SE7910189A patent/SE437200B/sv not_active IP Right Cessation
- 1979-12-14 DE DE19792950452 patent/DE2950452A1/de not_active Withdrawn
- 1979-12-14 JP JP16172579A patent/JPS55117256A/ja active Pending
- 1979-12-14 US US06/103,423 patent/US4266233A/en not_active Expired - Lifetime
- 1979-12-17 GB GB7943351A patent/GB2037078A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| FR2444340A1 (fr) | 1980-07-11 |
| GB2037078A (en) | 1980-07-02 |
| US4266233A (en) | 1981-05-05 |
| JPS55117256A (en) | 1980-09-09 |
| DE2950452A1 (de) | 1980-06-26 |
| SE7910189L (sv) | 1980-06-16 |
| IT7830894A0 (it) | 1978-12-15 |
| SE437200B (sv) | 1985-02-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19961227 |