IT1161869B - Dispositivo a semiconduttori e procedimento per la sua fabbricazione - Google Patents

Dispositivo a semiconduttori e procedimento per la sua fabbricazione

Info

Publication number
IT1161869B
IT1161869B IT19414/83A IT1941483A IT1161869B IT 1161869 B IT1161869 B IT 1161869B IT 19414/83 A IT19414/83 A IT 19414/83A IT 1941483 A IT1941483 A IT 1941483A IT 1161869 B IT1161869 B IT 1161869B
Authority
IT
Italy
Prior art keywords
procedure
manufacture
semiconductor device
semiconductor
Prior art date
Application number
IT19414/83A
Other languages
English (en)
Other versions
IT8319414A0 (it
Inventor
Masuda Masachika
Murakami Gen
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP57016233A external-priority patent/JPS58134453A/ja
Priority claimed from JP57016232A external-priority patent/JPS58134452A/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of IT8319414A0 publication Critical patent/IT8319414A0/it
Application granted granted Critical
Publication of IT1161869B publication Critical patent/IT1161869B/it

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/421Shapes or dispositions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • H10W74/016Manufacture or treatment using moulds
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
IT19414/83A 1982-02-05 1983-02-03 Dispositivo a semiconduttori e procedimento per la sua fabbricazione IT1161869B (it)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57016233A JPS58134453A (ja) 1982-02-05 1982-02-05 リ−ドフレ−ム
JP57016232A JPS58134452A (ja) 1982-02-05 1982-02-05 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
IT8319414A0 IT8319414A0 (it) 1983-02-03
IT1161869B true IT1161869B (it) 1987-03-18

Family

ID=26352512

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19414/83A IT1161869B (it) 1982-02-05 1983-02-03 Dispositivo a semiconduttori e procedimento per la sua fabbricazione

Country Status (7)

Country Link
KR (1) KR900001989B1 (it)
DE (1) DE3303165C2 (it)
GB (1) GB2115220B (it)
HK (1) HK70787A (it)
IT (1) IT1161869B (it)
MY (1) MY8700616A (it)
SG (1) SG36287G (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140742A (ja) * 1983-12-06 1985-07-25 フエアチアイルド カメラ アンド インストルメント コーポレーシヨン リードフレーム及びその実装方法
US4677526A (en) * 1984-03-01 1987-06-30 Augat Inc. Plastic pin grid array chip carrier
JP2634516B2 (ja) * 1991-10-15 1997-07-30 三菱電機株式会社 反転型icの製造方法、反転型ic、icモジュール
US6225685B1 (en) * 2000-04-05 2001-05-01 Advanced Micro Devices, Inc. Lead frame design for reduced wire sweep having a defined gap between tie bars and lead pins

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3926746A (en) * 1973-10-04 1975-12-16 Minnesota Mining & Mfg Electrical interconnection for metallized ceramic arrays
US4089575A (en) * 1976-09-27 1978-05-16 Amp Incorporated Connector for connecting a circuit element to the surface of a substrate
JPS5479563A (en) * 1977-12-07 1979-06-25 Kyushu Nippon Electric Lead frame for semiconductor
DE3061383D1 (en) * 1979-02-19 1983-01-27 Fujitsu Ltd Semiconductor device and method for manufacturing the same
US4195193A (en) * 1979-02-23 1980-03-25 Amp Incorporated Lead frame and chip carrier housing
US4289922A (en) * 1979-09-04 1981-09-15 Plessey Incorporated Integrated circuit package and lead frame

Also Published As

Publication number Publication date
GB8302730D0 (en) 1983-03-02
KR840003921A (ko) 1984-10-04
GB2115220A (en) 1983-09-01
HK70787A (en) 1987-10-09
IT8319414A0 (it) 1983-02-03
GB2115220B (en) 1985-11-06
DE3303165A1 (de) 1983-09-22
DE3303165C2 (de) 1993-12-09
SG36287G (en) 1987-07-24
KR900001989B1 (ko) 1990-03-30
MY8700616A (en) 1987-12-31

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970225