IT1204247B - Circuito logico cmos compatibile con circuiti logici ttl e con basso assorbimento di corrente nello stadio di ingresso - Google Patents

Circuito logico cmos compatibile con circuiti logici ttl e con basso assorbimento di corrente nello stadio di ingresso

Info

Publication number
IT1204247B
IT1204247B IT83624/86A IT8362486A IT1204247B IT 1204247 B IT1204247 B IT 1204247B IT 83624/86 A IT83624/86 A IT 83624/86A IT 8362486 A IT8362486 A IT 8362486A IT 1204247 B IT1204247 B IT 1204247B
Authority
IT
Italy
Prior art keywords
input stage
low current
cmos circuit
logic
current absorption
Prior art date
Application number
IT83624/86A
Other languages
English (en)
Other versions
IT8683624A0 (it
Inventor
Carlo Dallavalle
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT83624/86A priority Critical patent/IT1204247B/it
Publication of IT8683624A0 publication Critical patent/IT8683624A0/it
Priority to GB8712118A priority patent/GB2191355B/en
Priority to JP62132029A priority patent/JPS63153917A/ja
Priority to FR8707764A priority patent/FR2599912B1/fr
Priority to DE19873718769 priority patent/DE3718769A1/de
Application granted granted Critical
Publication of IT1204247B publication Critical patent/IT1204247B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
IT83624/86A 1986-06-04 1986-06-04 Circuito logico cmos compatibile con circuiti logici ttl e con basso assorbimento di corrente nello stadio di ingresso IT1204247B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT83624/86A IT1204247B (it) 1986-06-04 1986-06-04 Circuito logico cmos compatibile con circuiti logici ttl e con basso assorbimento di corrente nello stadio di ingresso
GB8712118A GB2191355B (en) 1986-06-04 1987-05-22 Ttl compatible cmos logic with low power dissipation in the input stage
JP62132029A JPS63153917A (ja) 1986-06-04 1987-05-29 入力段における電力消費が小さいトランジスタ−トランジスタ論理回路両立性ｃｍｏｓ論理回路
FR8707764A FR2599912B1 (fr) 1986-06-04 1987-06-03 Circuit logique cmos compatible ttl, a faible dissipation de puissance dans l'etage d'entree
DE19873718769 DE3718769A1 (de) 1986-06-04 1987-06-04 Ttl-kompatible cmos-logik mit geringem leistungsverlust in der eingangsstufe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT83624/86A IT1204247B (it) 1986-06-04 1986-06-04 Circuito logico cmos compatibile con circuiti logici ttl e con basso assorbimento di corrente nello stadio di ingresso

Publications (2)

Publication Number Publication Date
IT8683624A0 IT8683624A0 (it) 1986-06-04
IT1204247B true IT1204247B (it) 1989-03-01

Family

ID=11323308

Family Applications (1)

Application Number Title Priority Date Filing Date
IT83624/86A IT1204247B (it) 1986-06-04 1986-06-04 Circuito logico cmos compatibile con circuiti logici ttl e con basso assorbimento di corrente nello stadio di ingresso

Country Status (5)

Country Link
JP (1) JPS63153917A (it)
DE (1) DE3718769A1 (it)
FR (1) FR2599912B1 (it)
GB (1) GB2191355B (it)
IT (1) IT1204247B (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4763021A (en) * 1987-07-06 1988-08-09 Unisys Corporation CMOS input buffer receiver circuit with ultra stable switchpoint

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4593212A (en) * 1984-12-28 1986-06-03 Motorola, Inc. TTL to CMOS input buffer

Also Published As

Publication number Publication date
FR2599912B1 (fr) 1992-12-18
GB2191355B (en) 1989-12-20
IT8683624A0 (it) 1986-06-04
JPS63153917A (ja) 1988-06-27
GB2191355A (en) 1987-12-09
GB8712118D0 (en) 1987-06-24
DE3718769A1 (de) 1987-12-10
FR2599912A1 (fr) 1987-12-11

Similar Documents

Publication Publication Date Title
IT1239781B (it) Circuito e metodo per commutare selettivamente tensioni negative in circuiti integrati cmos
DE3471413D1 (en) Clocked differential cascode voltage switch logic circuit
DE3884058D1 (de) Hochspannungshalbleiter mit integrierter Niederspannungsschaltung.
GB2225913B (en) Cmos input level shifting circuit with temperature-compensating n-channel field effect transistor structure
EP0263078A3 (en) Logic interface circuit with high stability and low rest current
EP0111055A3 (en) Latch circuit with differential cascode current switch logic
DE3888703D1 (de) ECL-kompatible Eingangs-/Ausgangsschaltungen in CMOS-Technik.
DE59410347D1 (de) Integrierte Schaltungsanordnung mit Leistungsbauelement und Niederspannungsbauelementen
DE68910337D1 (de) Integrierte Schaltung mit Logikschaltungen und wenigstens einer Gegentaktstufe.
DE69128500D1 (de) Emittergekoppelte logische Schaltung
DE69126694D1 (de) Integrierte Halbleiterschaltung mit ECL-Eingangs- Ausgangspuffern
DE3379438D1 (en) Semiconductor integrated circuit device with output stage
DE68925158D1 (de) Verriegelungsschaltung in emittergekoppelter Logik
DE3750048D1 (de) Bauelement mit integrierter Schaltung und einer Zwischenschaltungsleitung.
IT1204247B (it) Circuito logico cmos compatibile con circuiti logici ttl e con basso assorbimento di corrente nello stadio di ingresso
IT1203893B (it) Circuito di amplificazione ad elevata precisione con piccolo ingombro e basso consumo di potenza per circuiti integrati.
IT1201859B (it) Circuito logico cmos
EP0293923A3 (en) Latch circuit constructed with mos transistors and shift register using the latch circuits
IT1201860B (it) Circuito logico cmos
DE69025567D1 (de) Integrierte CMOS-Ausgangsschaltung mit bipolaren Transistoren in der Ausgangsstufe
DE4326136B4 (de) Integrierte Schaltung mit Ausgangspufferschaltkreisen
IT1192461B (it) Perfezionamento nello schermaggio di circuiti elettrici
DE3375267D1 (en) Transition detector circuits and mos integrated circuits provided with such a detector circuit
KR930016753U (ko) 씨모스 인버터 회로
KR880007007U (ko) 집적 회로의 이중 소켓

Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970628