IT1204808B - Circuito di reset all'accensione per reti logiche in tecnologia mos,particolarmente per periferiche di microprocessori - Google Patents

Circuito di reset all'accensione per reti logiche in tecnologia mos,particolarmente per periferiche di microprocessori

Info

Publication number: IT1204808B
Authority: IT; Italy
Prior art keywords: reset circuit; mos technology; logic networks; ignition reset; microprocessor peripherals
Prior art date: 1986-02-18

Application number

IT19441/86A

Other languages

English (en)

Other versions

IT8619441A0 (it

Inventor

Alberto Aguti

Maurizio Gaibotti

Vittorio Masina

Original Assignee

Sgs Microelettronica Spa

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1986-02-18

Filing date

1986-02-18

Publication date

1989-03-10

1986-02-18 Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa

1986-02-18 Priority to IT19441/86A priority Critical patent/IT1204808B/it

1986-02-18 Publication of IT8619441A0 publication Critical patent/IT8619441A0/it

1987-02-13 Priority to US07/014,490 priority patent/US4797584A/en

1987-02-17 Priority to JP62034361A priority patent/JPH0810822B2/ja

1987-02-18 Priority to DE3705140A priority patent/DE3705140C2/de

1989-03-10 Application granted granted Critical

1989-03-10 Publication of IT1204808B publication Critical patent/IT1204808B/it

Links

Classifications

- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Electronic Switches (AREA)
Logic Circuits (AREA)

IT19441/86A 1986-02-18 1986-02-18 Circuito di reset all'accensione per reti logiche in tecnologia mos,particolarmente per periferiche di microprocessori IT1204808B (it)

Priority Applications (4)

Application Number	Priority Date	Filing Date	Title
IT19441/86A IT1204808B (it)	1986-02-18	1986-02-18	Circuito di reset all'accensione per reti logiche in tecnologia mos,particolarmente per periferiche di microprocessori
US07/014,490 US4797584A (en)	1986-02-18	1987-02-13	Power-on reset circuit for MOS logic devices
JP62034361A JPH0810822B2 (ja)	1986-02-18	1987-02-17	特にマイクロプロセツサの周辺装置用の、ｍｏｓ技術の論理回路のためのパワ−オンリセツテイング回路
DE3705140A DE3705140C2 (de)	1986-02-18	1987-02-18	In MOS-Technologie ausgeführte Einschalt-Rückstellschaltung für logische Schaltungsanordnungen, insbesondere für Peripherien von Mikroprozessoren

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
IT19441/86A IT1204808B (it)	1986-02-18	1986-02-18	Circuito di reset all'accensione per reti logiche in tecnologia mos,particolarmente per periferiche di microprocessori

Publications (2)

Publication Number	Publication Date
IT8619441A0 IT8619441A0 (it)	1986-02-18
IT1204808B true IT1204808B (it)	1989-03-10

Family

ID=11158008

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
IT19441/86A IT1204808B (it)	1986-02-18	1986-02-18	Circuito di reset all'accensione per reti logiche in tecnologia mos,particolarmente per periferiche di microprocessori

Country Status (4)

Country	Link
US (1)	US4797584A (it)
JP (1)	JPH0810822B2 (it)
DE (1)	DE3705140C2 (it)
IT (1)	IT1204808B (it)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JP2557411B2 (ja) *	1986-10-01	1996-11-27	株式会社東芝	半導体集積回路
US4874965A (en) *	1987-11-30	1989-10-17	Sgs Microelettronica S.P.A.	Circuital device for the power-on reset of digital integrated circuits in MOS technology
FR2625633B1 (fr) *	1987-12-30	1990-05-04	Sgs Thomson Microelectronics	Circuit de remise sous tension pour circuit integre en technologie mos
JPH0229115A (ja) *	1988-07-19	1990-01-31	Toshiba Corp	出力回路
US5030845A (en) *	1989-10-02	1991-07-09	Texas Instruments Incorporated	Power-up pulse generator circuit
US5115146A (en) *	1990-08-17	1992-05-19	Sgs-Thomson Microelectronics, Inc.	Power-on reset circuit for controlling test mode entry
US5121358A (en) *	1990-09-26	1992-06-09	Sgs-Thomson Microelectronics, Inc.	Semiconductor memory with power-on reset controlled latched row line repeaters
US5148051A (en) *	1990-12-14	1992-09-15	Dallas Semiconductor Corporation	Power up circuit
DE59107628D1 (de) *	1991-01-29	1996-05-02	Siemens Ag	Schaltungsanordnung zur Generierung eines Rücksetzsignals
US5109163A (en) *	1991-02-15	1992-04-28	Zilog, Inc.	Integrated power-on reset circuit
FR2684206B1 (fr) *	1991-11-25	1994-01-07	Sgs Thomson Microelectronics Sa	Circuit de lecture de fusible de redondance pour memoire integree.
US5323067A (en) *	1993-04-14	1994-06-21	National Semiconductor Corporation	Self-disabling power-up detection circuit
US5567993A (en) *	1994-06-23	1996-10-22	Dallas Semiconductor Corporation	Programmable power supply system and methods
US5537360A (en) *	1994-09-16	1996-07-16	Dallas Semiconductor Corporation	Programmable power supply systems and methods providing a write protected memory having multiple interface capability
US5959926A (en) *	1996-06-07	1999-09-28	Dallas Semiconductor Corp.	Programmable power supply systems and methods providing a write protected memory having multiple interface capability
US5828251A (en) *	1996-07-02	1998-10-27	Lucent Technologies Inc.	Power-up detector circuit
KR100253076B1 (ko) *	1997-05-02	2000-05-01	윤종용	순차 로직들을 위한 파워-온 리셋 회로(power-on reset circuit for sequential logics)
US5940345A (en) *	1997-12-12	1999-08-17	Cypress Semiconductor Corp.	Combinational logic feedback circuit to ensure correct power-on-reset of a four-bit synchronous shift register
KR100301252B1 (ko) *	1999-06-23	2001-11-01	박종섭	파워 온 리셋 회로
US6259284B1 (en) *	1999-12-22	2001-07-10	Hitachi America, Ltd.	Charge free power-on-reset circuit
US6744291B2 (en)	2002-08-30	2004-06-01	Atmel Corporation	Power-on reset circuit
US7868605B1 (en)	2007-07-02	2011-01-11	Altera Corporation	Mixed mode power regulator circuitry for memory elements
US7705659B1 (en) *	2007-07-02	2010-04-27	Altera Corporation	Power regulator circuitry with power-on-reset control
US7893566B2 (en) *	2009-03-13	2011-02-22	Fairchild Semiconductor Corporation	Power latch
JP6048026B2 (ja) *	2012-09-20	2016-12-21	富士通株式会社	電源回路及び電源装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
DE211027C (it) *
DE3330026A1 (de) *	1983-08-19	1985-02-28	Siemens AG, 1000 Berlin und 8000 München	Integrierte rs-flipflop-schaltung

1986
- 1986-02-18 IT IT19441/86A patent/IT1204808B/it active
1987
- 1987-02-13 US US07/014,490 patent/US4797584A/en not_active Expired - Lifetime
- 1987-02-17 JP JP62034361A patent/JPH0810822B2/ja not_active Expired - Lifetime
- 1987-02-18 DE DE3705140A patent/DE3705140C2/de not_active Expired - Fee Related

Also Published As

Publication number	Publication date
DE3705140C2 (de)	1995-04-06
JPH0810822B2 (ja)	1996-01-31
IT8619441A0 (it)	1986-02-18
DE3705140A1 (de)	1988-01-21
US4797584A (en)	1989-01-10
JPS62203416A (ja)	1987-09-08

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Legal Events

Date	Code	Title	Description
1999-10-27	TA	Fee payment date (situation as of event date), data collected since 19931001	Effective date: 19970227