IT1219238B - Dispositivo di traslazione dell'indirizzo per un memoria operativa di computer - Google Patents

Dispositivo di traslazione dell'indirizzo per un memoria operativa di computer

Info

Publication number
IT1219238B
IT1219238B IT67382/88A IT6738288A IT1219238B IT 1219238 B IT1219238 B IT 1219238B IT 67382/88 A IT67382/88 A IT 67382/88A IT 6738288 A IT6738288 A IT 6738288A IT 1219238 B IT1219238 B IT 1219238B
Authority
IT
Italy
Prior art keywords
address translation
translation device
operational memory
computer operational
computer
Prior art date
Application number
IT67382/88A
Other languages
English (en)
Other versions
IT8867382A0 (it
Inventor
Antonio Schinco
Giovanni Peveraro
Original Assignee
Olivetti & Co Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olivetti & Co Spa filed Critical Olivetti & Co Spa
Priority to IT67382/88A priority Critical patent/IT1219238B/it
Publication of IT8867382A0 publication Critical patent/IT8867382A0/it
Priority to EP19880310265 priority patent/EP0339157A3/en
Priority to JP63332727A priority patent/JPH01276350A/ja
Application granted granted Critical
Publication of IT1219238B publication Critical patent/IT1219238B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IT67382/88A 1988-04-26 1988-04-26 Dispositivo di traslazione dell'indirizzo per un memoria operativa di computer IT1219238B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT67382/88A IT1219238B (it) 1988-04-26 1988-04-26 Dispositivo di traslazione dell'indirizzo per un memoria operativa di computer
EP19880310265 EP0339157A3 (en) 1988-04-26 1988-11-01 Address translating apparatus for a computer memory
JP63332727A JPH01276350A (ja) 1988-04-26 1988-12-28 コンピュータメモリ用アドレス変換装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT67382/88A IT1219238B (it) 1988-04-26 1988-04-26 Dispositivo di traslazione dell'indirizzo per un memoria operativa di computer

Publications (2)

Publication Number Publication Date
IT8867382A0 IT8867382A0 (it) 1988-04-26
IT1219238B true IT1219238B (it) 1990-05-03

Family

ID=11301927

Family Applications (1)

Application Number Title Priority Date Filing Date
IT67382/88A IT1219238B (it) 1988-04-26 1988-04-26 Dispositivo di traslazione dell'indirizzo per un memoria operativa di computer

Country Status (3)

Country Link
EP (1) EP0339157A3 (it)
JP (1) JPH01276350A (it)
IT (1) IT1219238B (it)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3693165A (en) * 1971-06-29 1972-09-19 Ibm Parallel addressing of a storage hierarchy in a data processing system using virtual addressing
US4482952A (en) * 1980-12-15 1984-11-13 Nippon Electric Co., Ltd. Virtual addressing system using page field comparisons to selectively validate cache buffer data on read main memory data
JPS57138079A (en) * 1981-02-20 1982-08-26 Toshiba Corp Information processor
EP0732656B1 (en) * 1985-02-22 2003-08-06 Intergraph Corporation Cache MMU system
US4763244A (en) * 1986-01-15 1988-08-09 Motorola, Inc. Paged memory management unit capable of selectively supporting multiple address spaces

Also Published As

Publication number Publication date
EP0339157A3 (en) 1990-09-05
JPH01276350A (ja) 1989-11-06
IT8867382A0 (it) 1988-04-26
EP0339157A2 (en) 1989-11-02

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970429