IT1231913B - Procedimento di fabbricazione di transistori ad alta frequenza. - Google Patents

Procedimento di fabbricazione di transistori ad alta frequenza.

Info

Publication number
IT1231913B
IT1231913B IT8722392A IT2239287A IT1231913B IT 1231913 B IT1231913 B IT 1231913B IT 8722392 A IT8722392 A IT 8722392A IT 2239287 A IT2239287 A IT 2239287A IT 1231913 B IT1231913 B IT 1231913B
Authority
IT
Italy
Prior art keywords
high frequency
manufacturing procedure
frequency transistors
transistors
procedure
Prior art date
Application number
IT8722392A
Other languages
English (en)
Other versions
IT8722392A0 (it
Inventor
Raffaele Zambrano
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT8722392A priority Critical patent/IT1231913B/it
Publication of IT8722392A0 publication Critical patent/IT8722392A0/it
Priority to DE3854911T priority patent/DE3854911T2/de
Priority to EP88202260A priority patent/EP0313147B1/en
Priority to US07/259,261 priority patent/US5013672A/en
Application granted granted Critical
Publication of IT1231913B publication Critical patent/IT1231913B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/103—Mask, dual function, e.g. diffusion and oxidation
IT8722392A 1987-10-23 1987-10-23 Procedimento di fabbricazione di transistori ad alta frequenza. IT1231913B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT8722392A IT1231913B (it) 1987-10-23 1987-10-23 Procedimento di fabbricazione di transistori ad alta frequenza.
DE3854911T DE3854911T2 (de) 1987-10-23 1988-10-11 Verfahren zum Herstellen von Hochfrequenztransistoren
EP88202260A EP0313147B1 (en) 1987-10-23 1988-10-11 Manufacturing process for high-frequency transistors
US07/259,261 US5013672A (en) 1987-10-23 1988-10-18 Manufacturing process for high-frequency bipolar transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8722392A IT1231913B (it) 1987-10-23 1987-10-23 Procedimento di fabbricazione di transistori ad alta frequenza.

Publications (2)

Publication Number Publication Date
IT8722392A0 IT8722392A0 (it) 1987-10-23
IT1231913B true IT1231913B (it) 1992-01-15

Family

ID=11195666

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8722392A IT1231913B (it) 1987-10-23 1987-10-23 Procedimento di fabbricazione di transistori ad alta frequenza.

Country Status (4)

Country Link
US (1) US5013672A (it)
EP (1) EP0313147B1 (it)
DE (1) DE3854911T2 (it)
IT (1) IT1231913B (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5244821A (en) * 1991-06-07 1993-09-14 At&T Bell Laboratories Bipolar fabrication method
US5128272A (en) * 1991-06-18 1992-07-07 National Semiconductor Corporation Self-aligned planar monolithic integrated circuit vertical transistor process

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1492447A (en) * 1974-07-25 1977-11-16 Siemens Ag Semiconductor devices
DE2507366C3 (de) * 1975-02-20 1980-06-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Unterdrückung parasitärer Schaltungselemente
DE2605641C3 (de) * 1976-02-12 1979-12-20 Siemens Ag, 1000 Berlin Und 8000 Muenchen Hochfrequenztransistor und Verfahren zu seiner Herstellung
US4143455A (en) * 1976-03-11 1979-03-13 Siemens Aktiengesellschaft Method of producing a semiconductor component
US4199380A (en) * 1978-11-13 1980-04-22 Motorola, Inc. Integrated circuit method
US4498227A (en) * 1983-07-05 1985-02-12 Fairchild Camera & Instrument Corporation Wafer fabrication by implanting through protective layer

Also Published As

Publication number Publication date
US5013672A (en) 1991-05-07
DE3854911T2 (de) 1996-09-05
IT8722392A0 (it) 1987-10-23
EP0313147B1 (en) 1996-01-17
EP0313147A1 (en) 1989-04-26
DE3854911D1 (de) 1996-02-29

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971030