IT1251004B - Metodo per formare un micromodello sotto il limite di risoluzione di un processo fotolitografico - Google Patents

Metodo per formare un micromodello sotto il limite di risoluzione di un processo fotolitografico

Info

Publication number
IT1251004B
IT1251004B ITMI912235A ITMI912235A IT1251004B IT 1251004 B IT1251004 B IT 1251004B IT MI912235 A ITMI912235 A IT MI912235A IT MI912235 A ITMI912235 A IT MI912235A IT 1251004 B IT1251004 B IT 1251004B
Authority
IT
Italy
Prior art keywords
layer
resolution limit
photoresist
forming
photolithographic process
Prior art date
Application number
ITMI912235A
Other languages
English (en)
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI912235A0 publication Critical patent/ITMI912235A0/it
Publication of ITMI912235A1 publication Critical patent/ITMI912235A1/it
Application granted granted Critical
Publication of IT1251004B publication Critical patent/IT1251004B/it

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/696—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

Un metodo per formare un micromodello sotto il limite di risoluzione di un processo fotolitografico comprende le fasi di spalmare uno strato di fotoresist (11) su un materiale da incidere (10), esporre lo strato di fotoresist (11) usando una maschera sulla quale è formato un modello avente una larghezza di linea e una spaziatura sotto il limite di risoluzione dello strato di fotoresist (11), sviluppare lo strato di fotoresist esposto per formare scanalature (13) sulle superfici dello strato di fotoresist esposto, riempire le scanalature (13) con un materiale bloccante l'incisione (12) che è resistente all'incisione a ioni ossigeno-reattivi, incidere lo strato di fotoresist (11) mediante incisione a ioni ossigenoreattivi usando il materiale bloccante l'incisione (12) riempiente le scanalature (13) come maschera, e incidere il materiale usando il modello, che è fatto di uno strato di fotoresist e formato mediante il processo di incisione, come maschera.
ITMI912235A 1991-01-30 1991-08-09 Metodo per formare un micromodello sotto il limite di risoluzione di un processo fotolitografico IT1251004B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910001578A KR920015482A (ko) 1991-01-30 1991-01-30 광리소그라피의 한계해상도 이하의 미세패턴 형성방법

Publications (3)

Publication Number Publication Date
ITMI912235A0 ITMI912235A0 (it) 1991-08-09
ITMI912235A1 ITMI912235A1 (it) 1993-02-09
IT1251004B true IT1251004B (it) 1995-04-28

Family

ID=19310487

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI912235A IT1251004B (it) 1991-01-30 1991-08-09 Metodo per formare un micromodello sotto il limite di risoluzione di un processo fotolitografico

Country Status (6)

Country Link
JP (1) JPH04249311A (it)
KR (1) KR920015482A (it)
DE (1) DE4126635A1 (it)
FR (1) FR2672138A1 (it)
GB (1) GB2252449A (it)
IT (1) IT1251004B (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4236609A1 (de) * 1992-10-29 1994-05-05 Siemens Ag Verfahren zur Erzeugung einer Struktur in der Oberfläche eines Substrats
JP2803999B2 (ja) * 1993-11-10 1998-09-24 現代電子産業株式会社 半導体装置の微細パターン製造法
KR100229611B1 (ko) * 1996-06-12 1999-11-15 구자홍 액정표시장치의 제조방법
JP2000156377A (ja) 1998-11-19 2000-06-06 Murata Mfg Co Ltd レジストパターン及びその形成方法並びに配線パターンの形成方法
JP5655443B2 (ja) * 2010-09-06 2015-01-21 住友電気工業株式会社 無機化合物膜のエッチング方法および半導体光素子の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4634645A (en) * 1984-04-13 1987-01-06 Nippon Telegraph And Telephone Corporation Method of forming resist micropattern
JPS63114214A (ja) * 1986-09-11 1988-05-19 フェアチャイルド　セミコンダクタ　コーポレーション 二層マスクを使用するプラズマエッチング
US4878993A (en) * 1988-12-22 1989-11-07 North American Philips Corporation Method of etching thin indium tin oxide films

Also Published As

Publication number Publication date
ITMI912235A0 (it) 1991-08-09
DE4126635A1 (de) 1992-08-13
FR2672138A1 (fr) 1992-07-31
KR920015482A (ko) 1992-08-27
GB2252449A (en) 1992-08-05
ITMI912235A1 (it) 1993-02-09
JPH04249311A (ja) 1992-09-04
GB9117267D0 (en) 1991-09-25

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