IT1258717B - Dispositivo a semiconduttore e procedimento per la sua fabbricazione. - Google Patents

Dispositivo a semiconduttore e procedimento per la sua fabbricazione.

Info

Publication number
IT1258717B
IT1258717B ITTO920929A ITTO920929A IT1258717B IT 1258717 B IT1258717 B IT 1258717B IT TO920929 A ITTO920929 A IT TO920929A IT TO920929 A ITTO920929 A IT TO920929A IT 1258717 B IT1258717 B IT 1258717B
Authority
IT
Italy
Prior art keywords
region
standard cells
aluminum
semiconductor device
type
Prior art date
Application number
ITTO920929A
Other languages
English (en)
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITTO920929A0 publication Critical patent/ITTO920929A0/it
Publication of ITTO920929A1 publication Critical patent/ITTO920929A1/it
Application granted granted Critical
Publication of IT1258717B publication Critical patent/IT1258717B/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Viene fornita una moltitudine di celle standard (2) all'interno di una piastrina di circuito integrato (IC) (1), e viene realizzato uno strato di cablaggio di alluminio in una regione di cablaggio di alluminio (8) fornita tra due blocchi di celle standard (2) per connettere o blocchi di celle standard (2) elettricamente gli uni con gli altri.Vengono incorporate in un substrato della regione di cablaggio di alluminio (8) una regione epitassiale di tipo n (4), una regione di diffusione di tipo p (5) ed una regione di diffusione di tipo n (6), per, in questo modo, realizzare un dispositivo di valutazione costituito da un transistore bipolare non sotto la regione di cablaggio di alluminio (8). Viene fornito senza danno per il livello di integrazione un dispositivo a semiconduttore che ha la possibilità di valutare accuratamente la sua finitura per mezzo dell'ispezione del dispositivo di valutazione.
ITTO920929A 1991-11-25 1992-11-17 Dispositivo a semiconduttore e procedimento per la sua fabbricazione. IT1258717B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3308946A JP2721607B2 (ja) 1991-11-25 1991-11-25 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
ITTO920929A0 ITTO920929A0 (it) 1992-11-17
ITTO920929A1 ITTO920929A1 (it) 1994-05-17
IT1258717B true IT1258717B (it) 1996-02-27

Family

ID=17987160

Family Applications (1)

Application Number Title Priority Date Filing Date
ITTO920929A IT1258717B (it) 1991-11-25 1992-11-17 Dispositivo a semiconduttore e procedimento per la sua fabbricazione.

Country Status (4)

Country Link
US (1) US5489793A (it)
JP (1) JP2721607B2 (it)
DE (1) DE4239463C2 (it)
IT (1) IT1258717B (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213943A (ja) * 1996-01-29 1997-08-15 Mitsubishi Electric Corp パワーｍｏｓｆｅｔの製造方法
US6870206B2 (en) 2001-11-27 2005-03-22 Infineon Technologies Ag Semiconductor chip, fabrication method, and device for fabricating a semiconductor chip
DE10209073A1 (de) * 2002-02-28 2003-09-18 Infineon Technologies Ag Halbleiterchip, sowie Verfahren und Vorrichtung zur Herstellung des Halbleiterchips

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4197632A (en) * 1975-12-05 1980-04-15 Nippon Electric Co., Ltd. Semiconductor device
JPS5268376A (en) * 1975-12-05 1977-06-07 Nec Corp Semiconductor device
US4144493A (en) * 1976-06-30 1979-03-13 International Business Machines Corporation Integrated circuit test structure
US4413271A (en) * 1981-03-30 1983-11-01 Sprague Electric Company Integrated circuit including test portion and method for making
EP0278463B1 (en) * 1987-02-09 1994-07-27 Fujitsu Limited Gate array having transistor buried in interconnection region
JP2776549B2 (ja) * 1989-04-03 1998-07-16 日本電気アイシーマイコンシステム 株式会社 半導体集積回路
JPH03104169A (ja) * 1989-09-18 1991-05-01 Mitsubishi Electric Corp 半導体装置

Also Published As

Publication number Publication date
JPH05144906A (ja) 1993-06-11
ITTO920929A1 (it) 1994-05-17
US5489793A (en) 1996-02-06
DE4239463C2 (de) 1995-01-26
DE4239463A1 (en) 1993-05-27
JP2721607B2 (ja) 1998-03-04
ITTO920929A0 (it) 1992-11-17

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971129