IT1289524B1 - Cella di memoria per dispositivi di tipo eeprom e relativo processo di fabbricazione - Google Patents

Cella di memoria per dispositivi di tipo eeprom e relativo processo di fabbricazione

Info

Publication number
IT1289524B1
IT1289524B1 IT96MI002740A ITMI962740A IT1289524B1 IT 1289524 B1 IT1289524 B1 IT 1289524B1 IT 96MI002740 A IT96MI002740 A IT 96MI002740A IT MI962740 A ITMI962740 A IT MI962740A IT 1289524 B1 IT1289524 B1 IT 1289524B1
Authority
IT
Italy
Prior art keywords
memory cell
manufacturing process
type devices
related manufacturing
eeprom type
Prior art date
Application number
IT96MI002740A
Other languages
English (en)
Inventor
Bruno Vajana
Carlo Cremonesi
Roberta Bottini
Libera Giovanna Dalla
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT96MI002740A priority Critical patent/IT1289524B1/it
Priority to US08/996,921 priority patent/US6097057A/en
Publication of ITMI962740A1 publication Critical patent/ITMI962740A1/it
Application granted granted Critical
Publication of IT1289524B1 publication Critical patent/IT1289524B1/it
Priority to US09/534,253 priority patent/US6432762B1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
IT96MI002740A 1996-12-24 1996-12-24 Cella di memoria per dispositivi di tipo eeprom e relativo processo di fabbricazione IT1289524B1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT96MI002740A IT1289524B1 (it) 1996-12-24 1996-12-24 Cella di memoria per dispositivi di tipo eeprom e relativo processo di fabbricazione
US08/996,921 US6097057A (en) 1996-12-24 1997-12-23 Memory cell for EEPROM devices, and corresponding fabricating process
US09/534,253 US6432762B1 (en) 1996-12-24 2000-03-23 Memory cell for EEPROM devices, and corresponding fabricating process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT96MI002740A IT1289524B1 (it) 1996-12-24 1996-12-24 Cella di memoria per dispositivi di tipo eeprom e relativo processo di fabbricazione

Publications (2)

Publication Number Publication Date
ITMI962740A1 ITMI962740A1 (it) 1998-06-24
IT1289524B1 true IT1289524B1 (it) 1998-10-15

Family

ID=11375490

Family Applications (1)

Application Number Title Priority Date Filing Date
IT96MI002740A IT1289524B1 (it) 1996-12-24 1996-12-24 Cella di memoria per dispositivi di tipo eeprom e relativo processo di fabbricazione

Country Status (2)

Country Link
US (2) US6097057A (it)
IT (1) IT1289524B1 (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1045440A1 (en) * 1999-04-14 2000-10-18 STMicroelectronics S.r.l. Process of manufacture of a non volatile memory with electric continuity of the common source lines
US6933554B1 (en) * 2000-07-11 2005-08-23 Advanced Micro Devices, Inc. Recessed tunnel oxide profile for improved reliability in NAND devices
JP4809545B2 (ja) * 2001-05-31 2011-11-09 株式会社半導体エネルギー研究所 半導体不揮発性メモリ及び電子機器
JP2005183763A (ja) * 2003-12-22 2005-07-07 Toshiba Microelectronics Corp 不揮発性メモリを含む半導体装置の製造方法
JP5458526B2 (ja) * 2008-08-08 2014-04-02 富士通セミコンダクター株式会社 半導体装置及びその製造方法
KR101334844B1 (ko) * 2011-12-29 2013-12-05 주식회사 동부하이텍 싱글 폴리형 이이피롬과 그 제조 방법
FR3122943B1 (fr) * 2021-05-11 2023-11-24 St Microelectronics Rousset Circuit intégré comprenant une mémoire non-volatile du type EEPROM et procédé de fabrication correspondant.

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US35094A (en) * 1862-04-29 Faucet
IE39611B1 (en) * 1973-08-14 1978-11-22 Siemens Ag Improvements in or relating to two-phase charge coupled devices
US4574467A (en) * 1983-08-31 1986-03-11 Solid State Scientific, Inc. N- well CMOS process on a P substrate with double field guard rings and a PMOS buried channel
US5081054A (en) 1989-04-03 1992-01-14 Atmel Corporation Fabrication process for programmable and erasable MOS memory device
US5411904A (en) * 1990-11-19 1995-05-02 Sharp Kabushiki Kaisha Process for fabricating nonvolatile random access memory having a tunnel oxide film
IT1252214B (it) * 1991-12-13 1995-06-05 Sgs Thomson Microelectronics Procedimento per la definizione di porzioni di ossido sottile particolarmente per celle di memoria a sola lettura programmabili e cancellabile elettricamente.
JP2970158B2 (ja) * 1991-12-20 1999-11-02 日本電気株式会社 固体撮像装置の製造方法
US5346835A (en) * 1992-07-06 1994-09-13 Texas Instruments Incorporated Triple diffused lateral resurf insulated gate field effect transistor compatible with process and method
JPH0745730A (ja) * 1993-02-19 1995-02-14 Sgs Thomson Microelettronica Spa ２レベルのポリシリコンｅｅｐｒｏｍメモリ・セル並びにそのプログラミング方法及び製造方法、集積されたｅｅｐｒｏｍ記憶回路、ｅｅｐｒｏｍメモリ・セル及びそのプログラミング方法
JP3093096B2 (ja) * 1993-08-27 2000-10-03 シャープ株式会社 不揮発性メモリの製造方法
EP0655778A3 (en) * 1993-11-25 1996-01-03 Matsushita Electronics Corp Method of manufacturing semiconductor memory devices.
US5395773A (en) * 1994-03-31 1995-03-07 Vlsi Technology, Inc. MOSFET with gate-penetrating halo implant
US5468981A (en) * 1994-09-01 1995-11-21 Advanced Micro Devices, Inc. Self-aligned buried channel/junction stacked gate flash memory cell
US5501996A (en) * 1994-12-14 1996-03-26 United Microelectronics Corporation Method of manufacture of high coupling ratio single polysilicon floating gate EPROM or EEPROM cell
KR970701932A (ko) * 1995-01-17 1997-04-12 클라크 3세 존엠. 고전압 nmos 장치의 개선된 수행을 위한 연장된 드레인 영역에 인과 비소의 공통 주입(co-implantation of arsenic and phosphorus in extended drain region for improved performance of high voltage nmos device)
US5518942A (en) * 1995-02-22 1996-05-21 Alliance Semiconductor Corporation Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant
US5894146A (en) * 1995-02-28 1999-04-13 Sgs-Thomson Microelectronics, S.R.L. EEPROM memory cells matrix with double polysilicon level and relating manufacturing process
US5877054A (en) * 1995-06-29 1999-03-02 Sharp Kabushiki Kaisha Method of making nonvolatile semiconductor memory
US5908307A (en) * 1997-01-31 1999-06-01 Ultratech Stepper, Inc. Fabrication method for reduced-dimension FET devices
US6025635A (en) * 1997-07-09 2000-02-15 Advanced Micro Devices, Inc. Short channel transistor having resistive gate extensions
US5888853A (en) * 1997-08-01 1999-03-30 Advanced Micro Devices, Inc. Integrated circuit including a graded grain structure for enhanced transistor formation and fabrication method thereof

Also Published As

Publication number Publication date
ITMI962740A1 (it) 1998-06-24
US6432762B1 (en) 2002-08-13
US6097057A (en) 2000-08-01

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Legal Events

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0001 Granted