IT1289526B1 - Processo per la fabbricazione di celle di memoria a doppio livello di polisilicio per dispositivi di tipo eeprom - Google Patents

Processo per la fabbricazione di celle di memoria a doppio livello di polisilicio per dispositivi di tipo eeprom

Info

Publication number
IT1289526B1
IT1289526B1 IT96MI002742A ITMI962742A IT1289526B1 IT 1289526 B1 IT1289526 B1 IT 1289526B1 IT 96MI002742 A IT96MI002742 A IT 96MI002742A IT MI962742 A ITMI962742 A IT MI962742A IT 1289526 B1 IT1289526 B1 IT 1289526B1
Authority
IT
Italy
Prior art keywords
eeprom
dual
manufacture
memory cells
type devices
Prior art date
Application number
IT96MI002742A
Other languages
English (en)
Inventor
Libera Giovanna Dalla
Bruno Vajana
Roberta Bottini
Carlo Cremonesi
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT96MI002742A priority Critical patent/IT1289526B1/it
Priority to US08/996,922 priority patent/US5985718A/en
Publication of ITMI962742A1 publication Critical patent/ITMI962742A1/it
Application granted granted Critical
Publication of IT1289526B1 publication Critical patent/IT1289526B1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
IT96MI002742A 1996-12-24 1996-12-24 Processo per la fabbricazione di celle di memoria a doppio livello di polisilicio per dispositivi di tipo eeprom IT1289526B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT96MI002742A IT1289526B1 (it) 1996-12-24 1996-12-24 Processo per la fabbricazione di celle di memoria a doppio livello di polisilicio per dispositivi di tipo eeprom
US08/996,922 US5985718A (en) 1996-12-24 1997-12-23 Process for fabricating memory cells with two levels of polysilicon for devices of EEPROM type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT96MI002742A IT1289526B1 (it) 1996-12-24 1996-12-24 Processo per la fabbricazione di celle di memoria a doppio livello di polisilicio per dispositivi di tipo eeprom

Publications (2)

Publication Number Publication Date
ITMI962742A1 ITMI962742A1 (it) 1998-06-24
IT1289526B1 true IT1289526B1 (it) 1998-10-15

Family

ID=11375492

Family Applications (1)

Application Number Title Priority Date Filing Date
IT96MI002742A IT1289526B1 (it) 1996-12-24 1996-12-24 Processo per la fabbricazione di celle di memoria a doppio livello di polisilicio per dispositivi di tipo eeprom

Country Status (2)

Country Link
US (1) US5985718A (it)
IT (1) IT1289526B1 (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6346442B1 (en) 1999-02-04 2002-02-12 Tower Semiconductor Ltd. Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array
US6376308B1 (en) * 2000-01-19 2002-04-23 Advanced Micro Devices, Inc. Process for fabricating an EEPROM device having a pocket substrate region
US6440797B1 (en) 2001-09-28 2002-08-27 Advanced Micro Devices, Inc. Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory
JP2003309194A (ja) * 2002-04-18 2003-10-31 Nec Electronics Corp 半導体記憶装置とその製造方法
KR100471165B1 (ko) * 2002-05-07 2005-03-08 삼성전자주식회사 평탄하지 않은 게이트 절연막을 구비하는 비휘발성 메모리장치 및 그 제조 방법
US7067362B2 (en) * 2003-10-17 2006-06-27 Chartered Semiconductor Manufacturing Ltd. Integrated circuit with protected implantation profiles and method for the formation thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07335883A (ja) * 1994-06-15 1995-12-22 Toshiba Corp 半導体装置の製造方法
US5877054A (en) * 1995-06-29 1999-03-02 Sharp Kabushiki Kaisha Method of making nonvolatile semiconductor memory
US5789295A (en) * 1995-11-17 1998-08-04 Advanced Micro Devices, Inc. Method of eliminating or reducing poly1 oxidation at stacked gate edge in flash EPROM process
KR100199381B1 (ko) * 1996-02-09 1999-06-15 김영환 플래쉬 이이피롬 셀 제조 방법
US5702957A (en) * 1996-09-20 1997-12-30 Lsi Logic Corporation Method of making buried metallization structure

Also Published As

Publication number Publication date
ITMI962742A1 (it) 1998-06-24
US5985718A (en) 1999-11-16

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