IT1289933B1 - Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione - Google Patents
Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazioneInfo
- Publication number
- IT1289933B1 IT1289933B1 IT97MI000357A ITMI970357A IT1289933B1 IT 1289933 B1 IT1289933 B1 IT 1289933B1 IT 97MI000357 A IT97MI000357 A IT 97MI000357A IT MI970357 A ITMI970357 A IT MI970357A IT 1289933 B1 IT1289933 B1 IT 1289933B1
- Authority
- IT
- Italy
- Prior art keywords
- matrix
- manufacturing procedure
- triple well
- related manufacturing
- memory device
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000011159 matrix material Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT97MI000357A IT1289933B1 (it) | 1997-02-20 | 1997-02-20 | Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione |
| US09/027,343 US5990526A (en) | 1997-02-20 | 1998-02-20 | Memory device with a cell array in triple well, and related manufacturing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT97MI000357A IT1289933B1 (it) | 1997-02-20 | 1997-02-20 | Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ITMI970357A1 ITMI970357A1 (it) | 1998-08-20 |
| IT1289933B1 true IT1289933B1 (it) | 1998-10-19 |
Family
ID=11376088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT97MI000357A IT1289933B1 (it) | 1997-02-20 | 1997-02-20 | Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5990526A (it) |
| IT (1) | IT1289933B1 (it) |
Families Citing this family (40)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IL125604A (en) | 1997-07-30 | 2004-03-28 | Saifun Semiconductors Ltd | Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge |
| US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
| US6633496B2 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Symmetric architecture for memory cells having widely spread metal bit lines |
| US6633499B1 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Method for reducing voltage drops in symmetric array architectures |
| US6430077B1 (en) | 1997-12-12 | 2002-08-06 | Saifun Semiconductors Ltd. | Method for regulating read voltage level at the drain of a cell in a symmetric array |
| JP3523521B2 (ja) * | 1998-04-09 | 2004-04-26 | 松下電器産業株式会社 | Ｍｏｓトランジスタ対装置 |
| US6030871A (en) * | 1998-05-05 | 2000-02-29 | Saifun Semiconductors Ltd. | Process for producing two bit ROM cell utilizing angled implant |
| US6396741B1 (en) | 2000-05-04 | 2002-05-28 | Saifun Semiconductors Ltd. | Programming of nonvolatile memory cells |
| US6928001B2 (en) | 2000-12-07 | 2005-08-09 | Saifun Semiconductors Ltd. | Programming and erasing methods for a non-volatile memory cell |
| US6614692B2 (en) | 2001-01-18 | 2003-09-02 | Saifun Semiconductors Ltd. | EEPROM array and method for operation thereof |
| US6584017B2 (en) | 2001-04-05 | 2003-06-24 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
| US6677805B2 (en) | 2001-04-05 | 2004-01-13 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
| US6636440B2 (en) | 2001-04-25 | 2003-10-21 | Saifun Semiconductors Ltd. | Method for operation of an EEPROM array, including refresh thereof |
| US6643181B2 (en) | 2001-10-24 | 2003-11-04 | Saifun Semiconductors Ltd. | Method for erasing a memory cell |
| US6885585B2 (en) * | 2001-12-20 | 2005-04-26 | Saifun Semiconductors Ltd. | NROM NOR array |
| US6700818B2 (en) | 2002-01-31 | 2004-03-02 | Saifun Semiconductors Ltd. | Method for operating a memory device |
| US6975536B2 (en) * | 2002-01-31 | 2005-12-13 | Saifun Semiconductors Ltd. | Mass storage array and methods for operation thereof |
| US6917544B2 (en) | 2002-07-10 | 2005-07-12 | Saifun Semiconductors Ltd. | Multiple use memory chip |
| US6826107B2 (en) | 2002-08-01 | 2004-11-30 | Saifun Semiconductors Ltd. | High voltage insertion in flash memory cards |
| US7136304B2 (en) | 2002-10-29 | 2006-11-14 | Saifun Semiconductor Ltd | Method, system and circuit for programming a non-volatile memory array |
| US7178004B2 (en) | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
| US7142464B2 (en) | 2003-04-29 | 2006-11-28 | Saifun Semiconductors Ltd. | Apparatus and methods for multi-level sensing in a memory array |
| US7123532B2 (en) | 2003-09-16 | 2006-10-17 | Saifun Semiconductors Ltd. | Operating array cells with matched reference cells |
| US7317633B2 (en) | 2004-07-06 | 2008-01-08 | Saifun Semiconductors Ltd | Protection of NROM devices from charge damage |
| US7095655B2 (en) | 2004-08-12 | 2006-08-22 | Saifun Semiconductors Ltd. | Dynamic matching of signal path and reference path for sensing |
| US7638850B2 (en) | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
| US7535765B2 (en) | 2004-12-09 | 2009-05-19 | Saifun Semiconductors Ltd. | Non-volatile memory device and method for reading cells |
| CN1838328A (zh) | 2005-01-19 | 2006-09-27 | 赛芬半导体有限公司 | 擦除存储器阵列上存储单元的方法 |
| US8053812B2 (en) | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
| JP2007027760A (ja) | 2005-07-18 | 2007-02-01 | Saifun Semiconductors Ltd | 高密度不揮発性メモリアレイ及び製造方法 |
| US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
| US7221138B2 (en) | 2005-09-27 | 2007-05-22 | Saifun Semiconductors Ltd | Method and apparatus for measuring charge pump output current |
| US7352627B2 (en) | 2006-01-03 | 2008-04-01 | Saifon Semiconductors Ltd. | Method, system, and circuit for operating a non-volatile memory array |
| US7808818B2 (en) | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
| US7692961B2 (en) | 2006-02-21 | 2010-04-06 | Saifun Semiconductors Ltd. | Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection |
| US8253452B2 (en) | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
| US7760554B2 (en) | 2006-02-21 | 2010-07-20 | Saifun Semiconductors Ltd. | NROM non-volatile memory and mode of operation |
| US7638835B2 (en) | 2006-02-28 | 2009-12-29 | Saifun Semiconductors Ltd. | Double density NROM with nitride strips (DDNS) |
| US7701779B2 (en) | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
| US7605579B2 (en) | 2006-09-18 | 2009-10-20 | Saifun Semiconductors Ltd. | Measuring and controlling current consumption and output current of charge pumps |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4933736A (en) * | 1982-04-12 | 1990-06-12 | North American Philips Corporation, Signetics Division | Programmable read-only memory |
| JPS63278248A (ja) * | 1987-03-13 | 1988-11-15 | Fujitsu Ltd | ゲ−トアレイの基本セル |
| US5396100A (en) * | 1991-04-05 | 1995-03-07 | Hitachi, Ltd. | Semiconductor integrated circuit device having a compact arrangement of SRAM cells |
| KR0135798B1 (ko) * | 1994-08-17 | 1998-04-24 | 김광호 | 전류증폭형 마스크-롬 |
-
1997
- 1997-02-20 IT IT97MI000357A patent/IT1289933B1/it active IP Right Grant
-
1998
- 1998-02-20 US US09/027,343 patent/US5990526A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5990526A (en) | 1999-11-23 |
| ITMI970357A1 (it) | 1998-08-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted |