IT1291380B1 - Procedimenti di formazione di dispositivi a semiconduttore a canale- porta verticale aventi regioni di sorgente e di corpo autoallineate - Google Patents

Procedimenti di formazione di dispositivi a semiconduttore a canale- porta verticale aventi regioni di sorgente e di corpo autoallineate

Info

Publication number
IT1291380B1
IT1291380B1 IT97MI001192A ITMI971192A IT1291380B1 IT 1291380 B1 IT1291380 B1 IT 1291380B1 IT 97MI001192 A IT97MI001192 A IT 97MI001192A IT MI971192 A ITMI971192 A IT MI971192A IT 1291380 B1 IT1291380 B1 IT 1291380B1
Authority
IT
Italy
Prior art keywords
procedures
self
formation
semiconductor channel
body regions
Prior art date
Application number
IT97MI001192A
Other languages
English (en)
Inventor
Yong-Cheol Choi
Chang-Ki Jeon
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019960017409A external-priority patent/KR100218537B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI971192A0 publication Critical patent/ITMI971192A0/it
Publication of ITMI971192A1 publication Critical patent/ITMI971192A1/it
Application granted granted Critical
Publication of IT1291380B1 publication Critical patent/IT1291380B1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
IT97MI001192A 1996-05-22 1997-05-21 Procedimenti di formazione di dispositivi a semiconduttore a canale- porta verticale aventi regioni di sorgente e di corpo autoallineate IT1291380B1 (it)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019960017409A KR100218537B1 (ko) 1996-05-22 1996-05-22 트렌치 확산 모스 트랜지스터의 구조 및 제조 공정
US08/855,459 US5918114A (en) 1996-05-22 1997-05-13 Method of forming vertical trench-gate semiconductor devices having self-aligned source and body regions

Publications (3)

Publication Number Publication Date
ITMI971192A0 ITMI971192A0 (it) 1997-05-21
ITMI971192A1 ITMI971192A1 (it) 1998-11-21
IT1291380B1 true IT1291380B1 (it) 1999-01-08

Family

ID=26631856

Family Applications (1)

Application Number Title Priority Date Filing Date
IT97MI001192A IT1291380B1 (it) 1996-05-22 1997-05-21 Procedimenti di formazione di dispositivi a semiconduttore a canale- porta verticale aventi regioni di sorgente e di corpo autoallineate

Country Status (3)

Country Link
US (1) US5918114A (it)
JP (1) JP4077529B2 (it)
IT (1) IT1291380B1 (it)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180966B1 (en) * 1997-03-25 2001-01-30 Hitachi, Ltd. Trench gate type semiconductor device with current sensing cell
JP3502531B2 (ja) * 1997-08-28 2004-03-02 株式会社ルネサステクノロジ 半導体装置の製造方法
US6077744A (en) * 1999-02-22 2000-06-20 Intersil Corporation Semiconductor trench MOS devices
US6413822B2 (en) 1999-04-22 2002-07-02 Advanced Analogic Technologies, Inc. Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer
US6238981B1 (en) * 1999-05-10 2001-05-29 Intersil Corporation Process for forming MOS-gated devices having self-aligned trenches
DE19935442C1 (de) 1999-07-28 2000-12-21 Siemens Ag Verfahren zum Herstellen eines Trench-MOS-Leistungstransistors
KR100399583B1 (ko) * 1999-11-29 2003-09-26 한국전자통신연구원 자기 정렬 기술을 이용한 트렌치 게이트 전력 소자 제조방법
JP3773755B2 (ja) * 2000-06-02 2006-05-10 セイコーインスツル株式会社 縦形ｍｏｓトランジスタ及びその製造方法
US6649975B2 (en) * 2000-11-16 2003-11-18 Silicon Semiconductor Corporation Vertical power devices having trench-based electrodes therein
GB0101695D0 (en) * 2001-01-23 2001-03-07 Koninkl Philips Electronics Nv Manufacture of trench-gate semiconductor devices
GB0113143D0 (en) * 2001-05-29 2001-07-25 Koninl Philips Electronics Nv Manufacture of trench-gate semiconductor devices
DE10246389B4 (de) * 2002-10-04 2007-04-26 Infineon Technologies Ag Verfahren zum Herstellen eines Trench-Halbleiterbauelements
US8193579B2 (en) 2008-07-29 2012-06-05 Rohm Co., Ltd. Trench type semiconductor device and fabrication method for the same
JP5403966B2 (ja) * 2008-07-29 2014-01-29 ローム株式会社 トレンチ型半導体素子及びトレンチ型半導体素子の製造方法
JP5738094B2 (ja) * 2010-09-14 2015-06-17 セイコーインスツル株式会社 半導体装置の製造方法
US9006063B2 (en) * 2013-06-28 2015-04-14 Stmicroelectronics S.R.L. Trench MOSFET
CN108039372B (zh) * 2017-12-21 2021-12-07 上海领矽半导体有限公司 沟槽型垂直双扩散金属氧化物晶体管及其制作方法
CN108133894B (zh) * 2017-12-21 2021-02-26 自贡国晶科技有限公司 沟槽型垂直双扩散金属氧化物晶体管及其制作方法
JP7040315B2 (ja) * 2018-06-25 2022-03-23 住友電気工業株式会社 炭化珪素半導体装置の製造方法
CN111370463A (zh) * 2018-12-26 2020-07-03 深圳尚阳通科技有限公司 沟槽栅功率器件及其制造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4685196A (en) * 1985-07-29 1987-08-11 Industrial Technology Research Institute Method for making planar FET having gate, source and drain in the same plane
US5362665A (en) * 1994-02-14 1994-11-08 Industrial Technology Research Institute Method of making vertical DRAM cross point memory cell

Also Published As

Publication number Publication date
ITMI971192A1 (it) 1998-11-21
JPH09321303A (ja) 1997-12-12
ITMI971192A0 (it) 1997-05-21
US5918114A (en) 1999-06-29
JP4077529B2 (ja) 2008-04-16

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