IT1314122B1 - Dispositivo buffer a doppia tensione di alimentazione per applicazionia bassa tensione di alimentazione. - Google Patents

Dispositivo buffer a doppia tensione di alimentazione per applicazionia bassa tensione di alimentazione.

Info

Publication number
IT1314122B1
IT1314122B1 IT1999MI002576A ITMI992576A IT1314122B1 IT 1314122 B1 IT1314122 B1 IT 1314122B1 IT 1999MI002576 A IT1999MI002576 A IT 1999MI002576A IT MI992576 A ITMI992576 A IT MI992576A IT 1314122 B1 IT1314122 B1 IT 1314122B1
Authority
IT
Italy
Prior art keywords
buffer device
power buffer
double
low voltage
voltage power
Prior art date
Application number
IT1999MI002576A
Other languages
English (en)
Inventor
Vincenzo Dima
Lorenzo Bedarida
Antonino Geraci
Simone Bartoli
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT1999MI002576A priority Critical patent/IT1314122B1/it
Publication of ITMI992576A0 publication Critical patent/ITMI992576A0/it
Priority to US09/736,984 priority patent/US6320361B2/en
Publication of ITMI992576A1 publication Critical patent/ITMI992576A1/it
Application granted granted Critical
Publication of IT1314122B1 publication Critical patent/IT1314122B1/it

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
IT1999MI002576A 1999-12-13 1999-12-13 Dispositivo buffer a doppia tensione di alimentazione per applicazionia bassa tensione di alimentazione. IT1314122B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT1999MI002576A IT1314122B1 (it) 1999-12-13 1999-12-13 Dispositivo buffer a doppia tensione di alimentazione per applicazionia bassa tensione di alimentazione.
US09/736,984 US6320361B2 (en) 1999-12-13 2000-12-13 Buffer device with dual supply voltage for low supply voltage applications

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT1999MI002576A IT1314122B1 (it) 1999-12-13 1999-12-13 Dispositivo buffer a doppia tensione di alimentazione per applicazionia bassa tensione di alimentazione.

Publications (3)

Publication Number Publication Date
ITMI992576A0 ITMI992576A0 (it) 1999-12-13
ITMI992576A1 ITMI992576A1 (it) 2001-06-13
IT1314122B1 true IT1314122B1 (it) 2002-12-04

Family

ID=11384096

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1999MI002576A IT1314122B1 (it) 1999-12-13 1999-12-13 Dispositivo buffer a doppia tensione di alimentazione per applicazionia bassa tensione di alimentazione.

Country Status (2)

Country Link
US (1) US6320361B2 (it)
IT (1) IT1314122B1 (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7414891B2 (en) * 2007-01-04 2008-08-19 Atmel Corporation Erase verify method for NAND-type flash memories
US7638990B1 (en) * 2007-05-27 2009-12-29 Altera Corporation Techniques for power management on integrated circuits
US10707872B1 (en) * 2019-03-20 2020-07-07 Semiconductor Components Industries, Llc Digital buffer circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5105104A (en) * 1990-04-13 1992-04-14 Motorola, Inc. Self-adjusting precharge level circuit
US5886540A (en) * 1996-05-31 1999-03-23 Hewlett-Packard Company Evaluation phase expansion for dynamic logic circuits
US5903500A (en) * 1997-04-11 1999-05-11 Intel Corporation 1.8 volt output buffer on flash memories
US6078195A (en) * 1997-06-03 2000-06-20 International Business Machines Corporation Logic blocks with mixed low and regular Vt MOSFET devices for VLSI design in the deep sub-micron regime
JP3036479B2 (ja) * 1997-08-08 2000-04-24 日本電気株式会社 ダイナミック論理回路

Also Published As

Publication number Publication date
ITMI992576A1 (it) 2001-06-13
US6320361B2 (en) 2001-11-20
US20010019260A1 (en) 2001-09-06
ITMI992576A0 (it) 1999-12-13

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