IT1397603B1 - Trincee di isolamento per strati semiconduttori. - Google Patents
Trincee di isolamento per strati semiconduttori.Info
- Publication number
- IT1397603B1 IT1397603B1 ITVI2009A000302A ITVI20090302A IT1397603B1 IT 1397603 B1 IT1397603 B1 IT 1397603B1 IT VI2009A000302 A ITVI2009A000302 A IT VI2009A000302A IT VI20090302 A ITVI20090302 A IT VI20090302A IT 1397603 B1 IT1397603 B1 IT 1397603B1
- Authority
- IT
- Italy
- Prior art keywords
- trinces
- insulation
- layer semiconductors
- semiconductors
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
- H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ITVI2009A000302A IT1397603B1 (it) | 2009-12-21 | 2009-12-21 | Trincee di isolamento per strati semiconduttori. |
| US12/973,505 US20110175191A1 (en) | 2009-12-21 | 2010-12-20 | Isolation trenches for semiconductor layers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ITVI2009A000302A IT1397603B1 (it) | 2009-12-21 | 2009-12-21 | Trincee di isolamento per strati semiconduttori. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ITVI20090302A1 ITVI20090302A1 (it) | 2011-06-22 |
| IT1397603B1 true IT1397603B1 (it) | 2013-01-16 |
Family
ID=42101651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ITVI2009A000302A IT1397603B1 (it) | 2009-12-21 | 2009-12-21 | Trincee di isolamento per strati semiconduttori. |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20110175191A1 (it) |
| IT (1) | IT1397603B1 (it) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104377134B (zh) * | 2013-08-14 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | 射频横向扩散晶体管无缺陷深场氧隔离的成长方法 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4685198A (en) * | 1985-07-25 | 1987-08-11 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing isolated semiconductor devices |
| JPS6467945A (en) * | 1987-09-08 | 1989-03-14 | Mitsubishi Electric Corp | Wiring layer formed on buried dielectric and manufacture thereof |
| TW309647B (it) * | 1995-12-30 | 1997-07-01 | Hyundai Electronics Ind | |
| US6306727B1 (en) * | 1997-08-18 | 2001-10-23 | Micron Technology, Inc. | Advanced isolation process for large memory arrays |
| US6239002B1 (en) * | 1998-10-19 | 2001-05-29 | Taiwan Semiconductor Manufacturing Company | Thermal oxidizing method for forming with attenuated surface sensitivity ozone-teos silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer |
| EP1073112A1 (en) * | 1999-07-26 | 2001-01-31 | STMicroelectronics S.r.l. | Process for the manufacturing of a SOI wafer by oxidation of buried cavities |
| JP3746669B2 (ja) * | 2000-10-17 | 2006-02-15 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
| US7420250B2 (en) * | 2004-08-30 | 2008-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection device having light doped regions |
-
2009
- 2009-12-21 IT ITVI2009A000302A patent/IT1397603B1/it active
-
2010
- 2010-12-20 US US12/973,505 patent/US20110175191A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| ITVI20090302A1 (it) | 2011-06-22 |
| US20110175191A1 (en) | 2011-07-21 |
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