IT201700053902A1 - Metodo di bonding ibrido per wafer a semiconduttore e relativo dispositivo integrato tridimensionale - Google Patents

Metodo di bonding ibrido per wafer a semiconduttore e relativo dispositivo integrato tridimensionale

Info

Publication number
IT201700053902A1
IT201700053902A1 IT102017000053902A IT201700053902A IT201700053902A1 IT 201700053902 A1 IT201700053902 A1 IT 201700053902A1 IT 102017000053902 A IT102017000053902 A IT 102017000053902A IT 201700053902 A IT201700053902 A IT 201700053902A IT 201700053902 A1 IT201700053902 A1 IT 201700053902A1
Authority
IT
Italy
Prior art keywords
wafer
semiconductor
integrated
bonding method
hybrid bonding
Prior art date
Application number
IT102017000053902A
Other languages
English (en)
Inventor
Amicis Giovanni De
Monte Andrea Del
Cola Onorato Di
Original Assignee
Lfoundry Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lfoundry Srl filed Critical Lfoundry Srl
Priority to IT102017000053902A priority Critical patent/IT201700053902A1/it
Priority to PCT/IB2018/053472 priority patent/WO2018211447A1/en
Priority to US16/612,662 priority patent/US11127776B2/en
Priority to JP2020514786A priority patent/JP7309692B2/ja
Priority to EP18730856.4A priority patent/EP3625819B1/en
Priority to CN201880032623.3A priority patent/CN110678963B/zh
Publication of IT201700053902A1 publication Critical patent/IT201700053902A1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/018—Manufacture or treatment of image sensors covered by group H10F39/12 of hybrid image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/026—Wafer-level processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/809—Constructional details of image sensors of hybrid image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/011—Manufacture or treatment of pads or other interconnections to be direct bonded
    • H10W80/016—Cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips
IT102017000053902A 2017-05-18 2017-05-18 Metodo di bonding ibrido per wafer a semiconduttore e relativo dispositivo integrato tridimensionale IT201700053902A1 (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT102017000053902A IT201700053902A1 (it) 2017-05-18 2017-05-18 Metodo di bonding ibrido per wafer a semiconduttore e relativo dispositivo integrato tridimensionale
PCT/IB2018/053472 WO2018211447A1 (en) 2017-05-18 2018-05-17 Hybrid bonding method for semiconductor wafers and related three-dimensional integrated device
US16/612,662 US11127776B2 (en) 2017-05-18 2018-05-17 Hybrid bonding method for semiconductor wafers and related three-dimensional integrated device
JP2020514786A JP7309692B2 (ja) 2017-05-18 2018-05-17 半導体ウェハのハイブリッド接合方法及び関連する３次元集積デバイス
EP18730856.4A EP3625819B1 (en) 2017-05-18 2018-05-17 Hybrid bonding method for semiconductor wafers and related three-dimensional integrated device
CN201880032623.3A CN110678963B (zh) 2017-05-18 2018-05-17 半导体晶片的复合粘接方法及相关的三维集成器件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102017000053902A IT201700053902A1 (it) 2017-05-18 2017-05-18 Metodo di bonding ibrido per wafer a semiconduttore e relativo dispositivo integrato tridimensionale

Publications (1)

Publication Number Publication Date
IT201700053902A1 true IT201700053902A1 (it) 2018-11-18

Family

ID=59859555

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102017000053902A IT201700053902A1 (it) 2017-05-18 2017-05-18 Metodo di bonding ibrido per wafer a semiconduttore e relativo dispositivo integrato tridimensionale

Country Status (6)

Country Link
US (1) US11127776B2 (it)
EP (1) EP3625819B1 (it)
JP (1) JP7309692B2 (it)
CN (1) CN110678963B (it)
IT (1) IT201700053902A1 (it)
WO (1) WO2018211447A1 (it)

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US11830817B2 (en) * 2020-08-12 2023-11-28 Advanced Micro Devices, Inc. Creating interconnects between dies using a cross-over die and through-die vias
US20230050652A1 (en) * 2021-08-16 2023-02-16 Micron Technology, Inc. Elastic bonding layers for semiconductor die assemblies and associated systems and methods
CN119654696A (zh) * 2022-08-01 2025-03-18 三井化学株式会社 基板层叠体的制造方法及半导体装置
US12588486B2 (en) 2022-08-26 2026-03-24 Advanced Micro Devices, Inc. Connecting semicondcutor device assembly components using interconnect dies with spacer component coupled to a portion of an interconnect die
CN119866533A (zh) * 2022-09-20 2025-04-22 东京毅力科创株式会社 基板接合方法和接合基板
CN120615235A (zh) * 2023-02-03 2025-09-09 三井化学株式会社 半导体结构体及其制造方法
US20240387448A1 (en) * 2023-05-15 2024-11-21 Tokyo Electron Limited Roentgen integrated metrology for hybrid bonding process control in ultra high 3d integration
WO2025201786A1 (en) * 2024-03-27 2025-10-02 Asml Netherlands B.V. Method for bonding semiconductor substrates
EP4687171A1 (en) * 2024-07-31 2026-02-04 ASML Netherlands B.V. Method and apparatus for bonding substrates

Citations (2)

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US20150021785A1 (en) * 2013-07-16 2015-01-22 Taiwan Semiconductor Manufacturing Co., Ltd Hybrid bonding with through substrate via (tsv)
US20160190103A1 (en) * 2013-09-20 2016-06-30 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device and manufacturing method therefor

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US6097096A (en) * 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
EP1190277B1 (en) * 1999-06-10 2009-10-07 AlliedSignal Inc. Semiconductor having spin-on-glass anti-reflective coatings for photolithography
US6559543B1 (en) * 2001-11-16 2003-05-06 International Business Machines Corporation Stacked fill structures for support of dielectric layers
KR100744590B1 (ko) * 2002-03-29 2007-08-01 동경 엘렉트론 주식회사 하지 절연막의 형성 방법 및 반도체 제조 장치
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JP6460947B2 (ja) * 2015-09-16 2019-01-30 東京エレクトロン株式会社 基板処理方法、基板処理装置および記憶媒体

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US20150021785A1 (en) * 2013-07-16 2015-01-22 Taiwan Semiconductor Manufacturing Co., Ltd Hybrid bonding with through substrate via (tsv)
US20160190103A1 (en) * 2013-09-20 2016-06-30 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device and manufacturing method therefor

Also Published As

Publication number Publication date
JP7309692B2 (ja) 2023-07-18
EP3625819A1 (en) 2020-03-25
JP2020520562A (ja) 2020-07-09
US20200212086A1 (en) 2020-07-02
WO2018211447A1 (en) 2018-11-22
CN110678963A (zh) 2020-01-10
CN110678963B (zh) 2023-07-07
EP3625819B1 (en) 2021-06-30
US11127776B2 (en) 2021-09-21

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