IT201700082176A1 - Sistema di elaborazione, relativo circuito integrato e procedimento - Google Patents

Sistema di elaborazione, relativo circuito integrato e procedimento

Info

Publication number
IT201700082176A1
IT201700082176A1 IT102017000082176A IT201700082176A IT201700082176A1 IT 201700082176 A1 IT201700082176 A1 IT 201700082176A1 IT 102017000082176 A IT102017000082176 A IT 102017000082176A IT 201700082176 A IT201700082176 A IT 201700082176A IT 201700082176 A1 IT201700082176 A1 IT 201700082176A1
Authority
IT
Italy
Prior art keywords
procedure
integrated circuit
processing system
related integrated
processing
Prior art date
Application number
IT102017000082176A
Other languages
English (en)
Inventor
Roberto Colombo
Original Assignee
Stmicroelectronics Application Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stmicroelectronics Application Gmbh filed Critical Stmicroelectronics Application Gmbh
Priority to IT102017000082176A priority Critical patent/IT201700082176A1/it
Priority to EP18182223.0A priority patent/EP3432190B1/en
Priority to US16/039,103 priority patent/US10949570B2/en
Publication of IT201700082176A1 publication Critical patent/IT201700082176A1/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/44—Program or device authentication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/62—Protecting access to data via a platform, e.g. using keys or access control rules
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/84—Vehicles

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Bioethics (AREA)
  • General Health & Medical Sciences (AREA)
  • Storage Device Security (AREA)
IT102017000082176A 2017-07-19 2017-07-19 Sistema di elaborazione, relativo circuito integrato e procedimento IT201700082176A1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT102017000082176A IT201700082176A1 (it) 2017-07-19 2017-07-19 Sistema di elaborazione, relativo circuito integrato e procedimento
EP18182223.0A EP3432190B1 (en) 2017-07-19 2018-07-06 Processing system and related integrated circuit for handling password management
US16/039,103 US10949570B2 (en) 2017-07-19 2018-07-18 Processing system, related integrated circuit and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102017000082176A IT201700082176A1 (it) 2017-07-19 2017-07-19 Sistema di elaborazione, relativo circuito integrato e procedimento

Publications (1)

Publication Number Publication Date
IT201700082176A1 true IT201700082176A1 (it) 2019-01-19

Family

ID=60294332

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102017000082176A IT201700082176A1 (it) 2017-07-19 2017-07-19 Sistema di elaborazione, relativo circuito integrato e procedimento

Country Status (3)

Country Link
US (1) US10949570B2 (it)
EP (1) EP3432190B1 (it)
IT (1) IT201700082176A1 (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020208639A2 (en) * 2019-04-11 2020-10-15 Saferide Technologies Ltd A system and method for detection of anomalous controller area network (can) messages
IT202100007475A1 (it) 2021-03-26 2022-09-26 Stmicroelectronics Application Gmbh Sistema di elaborazione, relativo circuito integrato, dispositivo e procedimento
IT202100030332A1 (it) 2021-11-30 2023-05-30 Stmicroelectronics Application Gmbh Sistema di elaborazione, relativo circuito integrato, dispositivo e procedimento

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781793A (en) * 1991-04-16 1998-07-14 Hewlett-Packard Company Appratus for preventing changes of computer configuration data by unauthorized users
US20090158444A1 (en) * 2007-12-12 2009-06-18 Goss John R System and Method for Controlling Access to Addressable Integrated Circuits
US20130019305A1 (en) * 2011-07-15 2013-01-17 Standard Microsystems Corporation Method and system for controlling access to embedded nonvolatile memories

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3424547B2 (ja) * 1998-02-26 2003-07-07 株式会社日立製作所 液体クロマトグラフ
US6145085A (en) * 1998-04-30 2000-11-07 Compaq Computer Corporation Method and apparatus for providing remote access to security features on a computer network
US6510522B1 (en) * 1998-11-20 2003-01-21 Compaq Information Technologies Group, L.P. Apparatus and method for providing access security to a device coupled upon a two-wire bidirectional bus
US20030233534A1 (en) * 2002-06-12 2003-12-18 Adrian Bernhard Enhanced computer start-up methods
US9343177B2 (en) * 2013-02-01 2016-05-17 Apple Inc. Accessing control registers over a data bus
US20150331043A1 (en) * 2014-05-15 2015-11-19 Manoj R. Sastry System-on-chip secure debug
US9792435B2 (en) * 2014-12-30 2017-10-17 Battelle Memorial Institute Anomaly detection for vehicular networks for intrusion and malfunction detection
US9792229B2 (en) * 2015-03-27 2017-10-17 Intel Corporation Protecting a memory
IT201700062788A1 (it) 2017-06-08 2018-12-08 Stmicroelectronics Application Gmbh Sistema di elaborazione, relativo circuito integrato, dispositivo e procedimento
IT201700062830A1 (it) 2017-06-08 2018-12-08 Stmicroelectronics Application Gmbh Sistema di elaborazione, relativo circuito integrato, dispositivo e procedimento

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781793A (en) * 1991-04-16 1998-07-14 Hewlett-Packard Company Appratus for preventing changes of computer configuration data by unauthorized users
US20090158444A1 (en) * 2007-12-12 2009-06-18 Goss John R System and Method for Controlling Access to Addressable Integrated Circuits
US20130019305A1 (en) * 2011-07-15 2013-01-17 Standard Microsystems Corporation Method and system for controlling access to embedded nonvolatile memories

Also Published As

Publication number Publication date
US20190026498A1 (en) 2019-01-24
EP3432190A1 (en) 2019-01-23
US10949570B2 (en) 2021-03-16
EP3432190B1 (en) 2020-09-23

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