IT201700087174A1 - Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore - Google Patents

Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore

Info

Publication number
IT201700087174A1
IT201700087174A1 IT102017000087174A IT201700087174A IT201700087174A1 IT 201700087174 A1 IT201700087174 A1 IT 201700087174A1 IT 102017000087174 A IT102017000087174 A IT 102017000087174A IT 201700087174 A IT201700087174 A IT 201700087174A IT 201700087174 A1 IT201700087174 A1 IT 201700087174A1
Authority
IT
Italy
Prior art keywords
semiconductor
device manufacturing
corresponding device
semiconductor devices
devices
Prior art date
Application number
IT102017000087174A
Other languages
English (en)
Inventor
Samuele Sciarrillo
Ivan Venegoni
Paolo Colpani
Francesca Milanesi
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT102017000087174A priority Critical patent/IT201700087174A1/it
Priority to US16/048,123 priority patent/US10593625B2/en
Publication of IT201700087174A1 publication Critical patent/IT201700087174A1/it

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425Barrier, adhesion or liner layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/69Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • H10W20/039Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures also covering sidewalls of the conductive structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/074Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43Layouts of interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63Vias, e.g. via plugs
    • H10W70/635Through-vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49Adaptable interconnections, e.g. fuses or antifuses
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • H10W70/652Cross-sectional shapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01908Manufacture or treatment of bond pads using permanent auxiliary members, e.g. using alignment marks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01931Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01933Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01935Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01951Changing the shapes of bond pads
    • H10W72/01953Changing the shapes of bond pads by etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01951Changing the shapes of bond pads
    • H10W72/01955Changing the shapes of bond pads by using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/922Bond pads being integral with underlying chip-level interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/922Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/923Bond pads having multiple stacked layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/934Cross-sectional shape, i.e. in side view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/941Dispositions of bond pads
    • H10W72/9415Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/941Dispositions of bond pads
    • H10W72/942Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/40Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/43Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
IT102017000087174A 2017-07-28 2017-07-28 Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore IT201700087174A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT102017000087174A IT201700087174A1 (it) 2017-07-28 2017-07-28 Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore
US16/048,123 US10593625B2 (en) 2017-07-28 2018-07-27 Semiconductor device and a corresponding method of manufacturing semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102017000087174A IT201700087174A1 (it) 2017-07-28 2017-07-28 Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore

Publications (1)

Publication Number Publication Date
IT201700087174A1 true IT201700087174A1 (it) 2019-01-28

Family

ID=60628065

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102017000087174A IT201700087174A1 (it) 2017-07-28 2017-07-28 Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore

Country Status (2)

Country Link
US (1) US10593625B2 (it)
IT (1) IT201700087174A1 (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11031325B2 (en) * 2019-10-18 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Low-stress passivation layer
US20230307314A1 (en) * 2022-03-24 2023-09-28 Texas Instruments Incorporated Direct bond copper substrate with metal filled ceramic substrate indentations

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521970B1 (en) * 2000-09-01 2003-02-18 National Semiconductor Corporation Chip scale package with compliant leads
US20120193793A1 (en) * 2011-02-01 2012-08-02 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
CN206293434U (zh) * 2016-02-01 2017-06-30 意法半导体股份有限公司 半导体器件

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63249346A (ja) 1987-04-03 1988-10-17 Fujitsu Ltd 集積回路チップにおけるパツドとその形成方法
US5223454A (en) 1988-01-29 1993-06-29 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US5550068A (en) * 1990-11-05 1996-08-27 Nippon Telegraph And Telephone Corporation Process of fabricating a circuit element for transmitting microwave signals
AU7491598A (en) 1997-05-15 1998-12-08 Formfactor, Inc. Lithographically defined microelectronic contact structures
US5937320A (en) 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
US6228759B1 (en) 2000-05-02 2001-05-08 Advanced Micro Devices, Inc. Method of forming an alloy precipitate to surround interconnect to minimize electromigration
US6528412B1 (en) 2001-04-30 2003-03-04 Advanced Micro Devices, Inc. Depositing an adhesion skin layer and a conformal seed layer to fill an interconnect opening
US6756294B1 (en) 2002-01-30 2004-06-29 Taiwan Semiconductor Manufacturing Company Method for improving bump reliability for flip chip devices
JP3794403B2 (ja) 2003-10-09 2006-07-05 セイコーエプソン株式会社 半導体装置
US7427557B2 (en) 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
US7166905B1 (en) 2004-10-05 2007-01-23 Integrated Device Technology, Inc. Stacked paddle micro leadframe package
US7946331B2 (en) 2005-06-14 2011-05-24 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
US8148822B2 (en) 2005-07-29 2012-04-03 Megica Corporation Bonding pad on IC substrate and method for making the same
JP4247690B2 (ja) 2006-06-15 2009-04-02 ソニー株式会社 電子部品及その製造方法
US8264072B2 (en) 2007-10-22 2012-09-11 Infineon Technologies Ag Electronic device
JP2009231681A (ja) 2008-03-25 2009-10-08 Citizen Watch Co Ltd 半導体装置およびその製造方法
US8283209B2 (en) 2008-06-10 2012-10-09 Stats Chippac, Ltd. Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumps
TW201019440A (en) 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
WO2010075447A1 (en) 2008-12-26 2010-07-01 Megica Corporation Chip packages with power management integrated circuits and related techniques
US8946896B2 (en) 2008-12-31 2015-02-03 Stmicroelectronics, Inc. Extended liner for localized thick copper interconnect
US8389397B2 (en) 2010-09-14 2013-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing UBM undercut in metal bump structures
US8227333B2 (en) 2010-11-17 2012-07-24 International Business Machines Corporation Ni plating of a BLM edge for Pb-free C4 undercut control
JP2012114148A (ja) 2010-11-22 2012-06-14 Fujitsu Semiconductor Ltd 半導体装置の製造方法
US8298930B2 (en) * 2010-12-03 2012-10-30 International Business Machines Corporation Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof
JP2012204788A (ja) 2011-03-28 2012-10-22 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
CN103165481B (zh) 2011-12-13 2015-07-15 颀邦科技股份有限公司 凸块制造工艺及其结构
JP5948924B2 (ja) 2012-02-09 2016-07-06 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、回路装置、回路装置の製造方法、電子機器
US9147628B2 (en) 2012-06-27 2015-09-29 Infineon Technoloiges Austria AG Package-in-packages and methods of formation thereof
JP2014241320A (ja) 2013-06-11 2014-12-25 ソニー株式会社 半導体装置、半導体装置の製造方法
US9786633B2 (en) 2014-04-23 2017-10-10 Massachusetts Institute Of Technology Interconnect structures for fine pitch assembly of semiconductor structures and related techniques
US10804153B2 (en) 2014-06-16 2020-10-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method to minimize stress on stack via
US9165873B1 (en) 2014-07-28 2015-10-20 Texas Instruments Incorporated Semiconductor package having etched foil capacitor integrated into leadframe
US9224686B1 (en) 2014-09-10 2015-12-29 International Business Machines Corporation Single damascene interconnect structure
JP6484490B2 (ja) 2015-04-10 2019-03-13 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR102379165B1 (ko) 2015-08-17 2022-03-25 삼성전자주식회사 Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법
US10541204B2 (en) * 2015-10-20 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure and method of forming the same
ITUB20161121A1 (it) 2016-02-26 2017-08-26 St Microelectronics Srl Procedimento per integrare condensatori in dispositivi a seminconduttore e corrispondente dispositivo

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521970B1 (en) * 2000-09-01 2003-02-18 National Semiconductor Corporation Chip scale package with compliant leads
US20120193793A1 (en) * 2011-02-01 2012-08-02 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
CN206293434U (zh) * 2016-02-01 2017-06-30 意法半导体股份有限公司 半导体器件

Also Published As

Publication number Publication date
US20190035741A1 (en) 2019-01-31
US10593625B2 (en) 2020-03-17

Similar Documents

Publication Publication Date Title
IT201900024292A1 (it) Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente
IT201700055987A1 (it) Procedimento per fabbricare dispositivi a semiconduttore e corrispondente prodotto
JP2017199900A5 (ja) 半導体装置の作製方法
DE112017007068T8 (de) Halbleitervorrichtung
KR101748949B9 (ko) 반도체 메모리 소자 및 이의 제조 방법
SG10201905840VA (en) Semiconductor device and manufacturing method thereof
JP2016027652A5 (ja) 半導体装置、及び電子機器
JP2017130655A5 (ja) 半導体装置及び電子機器
GB2573215B (en) Semiconductor manufacturing method and semiconductor manufacturing device
ITUB20161081A1 (it) Dispositivo a semiconduttore con regione conduttiva sepolta, e metodo di fabbricazione del dispositivo a semiconduttore
SG11202012288PA (en) Semiconductor device and method of manufacturing same
ITUB20160027A1 (it) Procedimento per produrre dispositivi a semiconduttore e corrispondente dispositivo
KR102220445B9 (ko) 반도체 소자 및 그 제조 방법
JP2017146968A5 (ja) 半導体装置、電子機器、半導体ウェハ
DE102018115474A8 (de) Halbleitervorrichtungen
IL274331A (en) Burning method and semiconductor manufacturing method
GB2562918B (en) Semiconductor device and method of manufacturing semiconductor device
EP3869561A4 (en) SEMICONDUCTOR ELEMENT AND ITS MANUFACTURING PROCESS
EP3627548A4 (en) SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR MODULE
IT201900024259A1 (it) Dispositivo a semiconduttore e corrispondente procedimento
EP3439023A4 (en) SEMICONDUCTOR COMPONENT MANUFACTURING METHOD
GB2589484B (en) Semiconductor device and method of manufacturing semiconductor device
IT201900022632A1 (it) Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente
ITUA20163031A1 (it) Dispositivo a semiconduttore e corrispondente procedimento
EP3576135A4 (en) SEMICONDUCTOR DEVICE MANUFACTURING PROCESS