IT201900007386A1 - DC-DC converter - Google Patents

Description

DESCRIPTION

Attached to a patent application for INDUSTRIAL INVENTION having the title

"DC-DC converter"

Technical field of the invention

The present invention generally relates to the electronics sector. More particularly, the present invention relates to a DC-DC converter.

Known technique

A DC-DC converter is an electronic circuit that converts a direct current source (DC = direct current) from one voltage level to another.

Nowadays DC-DC converters are used for example in portable electronic devices, such as smartphones and portable personal computers, in order to convert the voltage level generated by the supply battery into one or more different voltage levels in able to correctly power the electronic components mounted on the electronic boards inside the portable electronic devices.

Modern DC-DC converters convert the voltage level by first converting from a direct voltage level to a high frequency alternating voltage (AC) by means of a transformer in order to change the voltage level, then perform a rectification of the alternating voltage in order to generate a direct voltage of a different level.

Furthermore, modern DC-DC converters carry out the conversion using switching techniques, which allow to significantly increase (compared to linear voltage regulators) efficiency, reduce the space occupied because they use smaller electronic components and also have fewer problems of thermal dissipation. .

Switching-type DC-DC converters (known as "switched mode DC-DC converters") temporarily store electrical energy in a magnetic storage component (inductor, transformer) or electrical storage component (a capacitor) and then release the electrical energy accumulated at a different voltage level.

To effect an efficient switching, electronic devices are used which carry out the switching with fast rise and fall times, such as for example power FET transistors.

Some DC-DC converters are also bidirectional, i.e. the two ports of the converter can be one input and the other output or vice versa, where the two ports operate at different rated voltages and therefore are referred to as the HV high voltage port ( high voltage = high voltage) and leads to low voltage LV (low voltage = low voltage).

The power transfer between the input and output doors is called as follows:

- "buck" if the input port is the high voltage HV one and the output port is the low voltage LV one,

- "boost" if the input port is the low voltage LV one and the output port is the high voltage HV one.

Bidirectional DC-DC converters are for example used in hybrid thermal-electric motor vehicles that use braking to recover energy to recharge the battery that powers the electric motor.

Switching type DC-DC converters with magnetic storage periodically accumulate energy in the magnetic field of an inductor or transformer with a switching frequency between a few kHz and 10 MHz, then the energy accumulated in the inductor or transformer magnetic field is released with the same switching frequency.

The amount of power that is transferred to the load connected to the DC-DC converter can be easily controlled by varying the duty cycle of the charging current of the inductor or the charging voltage of the transformer, where the duty cycle is the ratio of the closing time interval and the duration of a period.

EP 1677410 describes a switching type bidirectional DC-DC converter that uses a transformer for the accumulation and release of energy in order to convert the voltage level.

The DC-DC converter described in EP 1677410 uses a cutting circuit 70 (see Fig. 1) to prevent voltage peaks being generated on the low voltage side, which would cause an efficiency reduction and could even cause the breakage of switches on the low voltage side of the DC-DC converter; the operation of the cutting circuit 70 is therefore controlled by a control unit 72 which generates suitable signals.

The DC-DC converter of EP 1677410 has the disadvantage that the cutting circuit control unit 72 70 is too complex.

Furthermore, the DC-DC converter of EP 1677410 has the disadvantage that, when it operates in the boost mode in which it is such as to increase the value of the continuous output voltage with respect to the input one, in the absence of voltage from the voltage generator 10 on the on the high voltage side, it does not allow the regulation of the load current towards the same voltage generator 10.

Brief summary of the invention

The present invention relates to a DC-DC converter as defined in the attached claim 1 and to its preferred embodiments described in the dependent claims 2 to 8.

The Applicant has perceived that the DC-DC converter according to the present invention has the following advantages:

- in addition to the buck and boost modes, it can operate in a further mode called "boost-limit" in which the input port is the low voltage LV one and the output port is the high voltage HV one, in which the '' HV high voltage is much lower than nominal or close to zero;

- in the boost-limit operating mode, it allows to limit the value of the load current towards the high voltage generator;

- in the buck operating mode, it allows to limit the value of reverse overvoltages in the rectification circuit of the low voltage side;

- in the buck operating mode, in case of failure of a component on the low voltage side (for example, a switch), it prevents the low voltage battery from being discharged;

- use simpler piloting schemes.

The present invention also relates to a power supply and control system as defined in the attached claim 9.

The present invention also relates to an electric motor or a hybrid motor vehicle of the electric / thermal type as defined in the attached claim 10.

Brief description of the drawings

Further features and advantages of the invention will emerge from the following description of a preferred embodiment and its variants provided by way of example with reference to the attached drawings, in which:

- Figure 1 shows a block diagram of a DC-DC converter according to a first embodiment of the invention;

- Figure 2A shows a block diagram of a DC-DC converter based on a second embodiment of the invention;

- Figure 2B shows a block diagram of a DC-DC converter based on a variant of the second embodiment of the invention; - Figure 3A shows a block diagram of a DC-DC converter according to a third embodiment of the invention;

- Figure 3B shows a block diagram of a DC-DC converter according to a variant of the third embodiment of the invention - Figure 4 schematically shows a power supply and control system which includes, alternatively, the DC-DC converter of the Figures 1, 2A, 2B, 3A, 3B;

- Figures 5A-5D schematically show a possible trend of some signals generated in a period of the "boost" operating mode in the DC-DC converter of Figures 3A-3B and in the system of Figure 4;

- Figures 6A-6D schematically show a possible trend of some signals generated in a period of the “buck” operating mode in the DC-DC converter of Figures 3A-3B and in the system of Figure 4;

- Figures 7A-7D schematically show a possible trend of some signals generated in a period of the "boostlimit" operating mode in the DC-DC converter of Figures 3A-3B and in the system of Figure 4.

Detailed description of the invention

It should be noted that in the following description identical or similar blocks, components or modules are indicated in the figures with the same numerical references, even if they are shown in different embodiments of the invention.

With reference to Figure 1, a DC-DC (DC = Direct Current) converter 1 is shown according to a first embodiment of the invention.

The DC-DC converter 1 performs a voltage conversion between two different direct voltage levels, indicated with the first direct voltage level ∆HV (also indicated with "high voltage") and with the second direct voltage level ∆LV (also indicated with "low voltage").

Furthermore, the DC-DC converter 1 is of the bidirectional type, is equipped with transformer insulation with a transformation ratio N and is capable of operating in three possible modes:

- a "buck" operating mode (direction from left to right of Figure 1 in the reading direction), in which the DC-DC converter 1 converts the direct voltage level from high voltage ∆HV to low voltage ∆ LV, where the low voltage ∆LV is less than ∆HV / N (for example ∆HV = 240 V, N = 6, ∆LV = 12 V);

- a "boost" operating mode (direction from right to left of Figure 1 in the reading direction), in which the DC-DC converter 1 converts the direct voltage level from low voltage ∆LV to high voltage ∆ HV, being ∆HV / N greater than ∆LV (for example ∆LV = 12 V, N = 6, ∆HV = 360 V);

- a "boost-limit" operating mode (direction from right to left of Figure 1 in the reading direction), in which the DC-DC converter 1 converts the direct voltage level from low voltage ∆LV to high voltage ∆HV, being ∆HV / N less than ∆LV (for example ∆LV = 12 V, N = 6, ∆HV = 6 V).

The DC-DC converter 1 comprises a first input / output terminal HV + and a second input / output terminal HV-, in which the DC high voltage level ∆HV is the potential difference between the first input / output terminal. HV + output and the second HV- input / output terminal; the first input / output terminal HV + is therefore able to receive / generate the upper value of the high direct voltage level ∆HV and the second input / output terminal HV- is able to receive / generate the lower value of the level of DC high voltage ∆HV.

The DC-DC converter 1 further comprises a third input / output terminal LV + and a fourth input / output terminal LV-, in which the DC low voltage level ∆LV is the potential difference between the third terminal of LV + input / output and the fourth LV- input / output terminal; the third input / output terminal LV + is therefore able to receive / generate the upper value of the low direct voltage level ∆LV and the fourth input / output terminal LV- is able to receive / generate the lower value of the level of DC low voltage ∆LV.

The electrical and electronic components that make up the DC-DC converter 1 are electrically connected as shown in Figure 1.

The DC-DC converter 1 comprises a high-voltage portion and a low-voltage portion separated from each other by a transformer 10, in which the high-voltage portion is shown in the left-hand side of Figure 1 (with respect to the reading direction of the Figure 1) and the low voltage portion is shown on the right side of Figure 1.

The term "high voltage" means a positive voltage level ∆HV lower than a first maximum value defined ∆HVmax, that is 0 V <∆HV <∆HVmax.

The term "low voltage" means a positive voltage level ∆LV lower than a second maximum defined value ∆LVmax, in which the second maximum defined value ∆LVmax is lower than the first maximum defined value ∆HVmax, that is 0 V <∆ LV <∆LVmax <∆HVmax.

For example, ∆HVmax = 400 V and ∆LVmax = 14 V, which results in 0 V <∆HV <400 V and 0 V <∆LV <14 V.

In particular, the high voltage portion of the DC-DC converter 1 comprises:

- a full bridge rectifier 5 comprising four diodes DS1, DS2, DS3, DS4;

- four switches S1, S2, S3, S4 having an H bridge topology; - a resonance inductor L_res;

- a pair of cut-off diodes D1, D2;

- a primary winding 10.1 of a transformer 10.

The low voltage portion of the DC-DC converter 1 comprises: - a secondary winding 10.2 of the transformer 10;

- a synchronous rectification circuit 11;

- two switches S5, S6;

- an output filter comprising a first inductor L1, a second inductor L2 and a capacitor C5;

- a capacity switch S10;

- a recirculation diode D3.

The transformer 10 has the function of converting a primary voltage Vpr at the ends of the primary winding 10.1 into a secondary voltage Vsec at the ends of the secondary winding 10.2 having a lower value than the primary voltage Vpr; vice versa, the transformer 10 also has the function of effecting a conversion of the secondary voltage Vsec into the primary voltage Vpr having a value greater than the secondary voltage Vsec.

The transformer 10 therefore comprises the primary winding 10.1, the secondary winding 10.2 and a magnetic core 10.3 for inductively coupling the primary winding 10.1 with the secondary winding 10.2, in which the voltage transformation ratio between the primary winding 10.1 and the secondary winding 10.2 is equal to a value N> 0 (for example, N = 6).

The primary winding 10.1 includes a first terminal connected to the full bridge rectifier 5 (as will be explained further below) and includes a second terminal connected to the resonance inductor L_res.

The secondary winding 10.2 comprises a first terminal (also referred to as node N1) connected to a first terminal of the rectification circuit 11 and connected to the first inductor L1; the secondary winding 10.2 also includes a second terminal (also referred to as node N2) connected to a second terminal of the rectification circuit 11 and connected to the second inductor L2.

The diodes DS1, DS2, DS3, DS4 of the full bridge rectifier 5 have the function of rectifying the primary voltage Vpr generated across the primary winding 10.1 during the boost operating mode and during the boost-limit operating mode.

During the buck operating mode, on the other hand, the diodes DS1, DS2, DS3, DS4 are directly biased in the short dead time necessary to switch the opening / closing state of switches S1, S2, S3 and S4, otherwise the diodes DS1, DS2 , DS3, DS4 are inversely polarized.

The resonance inductor L_res has the function, in the buck operating mode, of allowing zero voltage switching (ZVS, zero voltage switching) of switches S1, S2, S3 and S4, thanks to the resonance with the parasitic capacitances of switches S1 , S2, S3 and S4 themselves.

The resonance inductor L_res comprises a first terminal connected to the anode terminal of the diode DS1 and to the cathode terminal of the diode DS4 and includes a second terminal connected to the second terminal of the primary winding 10.1.

It should be noted that for the purposes of the explanation of the invention the resonance inductor L_res has been shown as a separate element, but the resonance inductor L_res can also be integrated in the transformer 10, being the resonance inductor L_res constituted by the inductance dispersion of the primary winding 10.1 of the transformer 10 itself.

The four switches S1, S2, S3, S4 have an H bridge topology, which consists of two branches, in which the first branch is formed by the series connection of switches S1 and S4, while the second branch is formed by the connection series of switches S2 and S3.

Furthermore, the four switches S1, S2, S3, S4 are connected in parallel to the four diodes DS1, DS2, DS3, DS4 respectively.

In the buck operating mode, the four switches S1, S2, S3, S4 switch between a closed position in which they are substantially equivalent to a short circuit and an open position in which they are equivalent to an open circuit.

During the boost and boost-limit operating modes, on the other hand, switches S1, S2, S3, S4 are in the open position.

In the buck operating mode, the four switches S1, S2, S3, S4 have the function of alternately connecting / disconnecting the high direct voltage level ∆HV to / from the primary winding 10.1, suitably controlling the generation of the primary voltage Vpr across the primary winding 10.1 and therefore the secondary voltage Vsec across the secondary winding 10.2; by means of the commutation of the four switches S1, S2, S3, S4, during the buck operation mode the low direct voltage level ∆LV is connected / disconnected alternatively to / from the first and second inductors L1, L2, as will be explained further on detail later.

The switches S1, S2, S3, S4 are made for example with MOSFET transistors or bipolar transistors.

The DS1 diode is connected in parallel to the S1 switch, the DS2 diode is connected in parallel to the S2 switch, the DS3 diode is connected in parallel to the S3 switch and the DS4 diode is connected in parallel to the S4 switch.

It should be noted that for the purposes of the explanation of the invention the diodes DS1, DS2, DS3 and DS4 have been considered as separate elements, but the diodes DS1, DS2, DS3 and DS4 can also be the body diodes of the possible MOSFET embodiment respectively of the switches S1, S2, S3 and S4.

The switch S1 includes a first terminal I connected to the first input / output terminal HV + and to the cathode terminal of the diode DS1; the switch S1 also includes a second terminal O connected to the anode terminal of the diode DS1, connected to the switch S4, connected to the diode DS4 and connected to the first terminal of the resonance inductor L_res.

The switch S1 also comprises a control terminal C adapted to receive a first PWM1A signal which controls the periodic opening and closing of the switch S1 in the buck operating mode and keeps the switch S1 open in the boost and boost operating mode. -limit.

Switch S2 includes a first terminal I connected to the first terminal I of the first switch S1 (and therefore connected to the first HV + input / output terminal) and connected to the cathode terminal of the diode DS2; the switch S2 also includes a second terminal O connected to the anode terminal of the diode DS2, connected to the first terminal of the primary winding 10.1, connected to the switch S3 and connected to the diode DS3.

The switch S2 also comprises a control terminal C adapted to receive a second PWM2A signal which controls the periodic opening and closing of the switch S2 in the buck operating mode and keeps the S2 switch open in the boost and boost operating mode. -limit.

The switch S4 includes a first terminal I connected to the cathode terminal of the diode DS4 and connected to the second terminal O of the switch S1 (and therefore connected to the first terminal of the resonance inductor L_res); the switch S4 also includes a second terminal O connected to the anode terminal of the diode DS4, connected to the second input / output terminal HV-, connected to the switch S3 and connected to the diode DS3.

The switch S4 also comprises a control terminal C adapted to receive a fourth PWM1B signal which controls the periodic opening and closing of the switch S4 in the buck operating mode and keeps the S4 switch open in the boost and boost operating mode. -limit.

The switch S3 includes a first terminal I connected to the cathode terminal of the diode DS3 and connected to the second terminal O of the switch S2 (and therefore connected to the first terminal of the primary winding 10.1); the switch S3 also includes a second terminal O connected to the anode terminal of the diode DS3 and connected to the second terminal O of the switch S4 (and therefore connected to the second input / output terminal HV-).

The switch S3 also comprises a control terminal C adapted to receive a third PWM2B signal which controls the periodic opening and closing of the switch S3 in the buck operating mode and keeps the S3 switch open in the boost and boost operating mode. -limit.

In the boost and boost-limit operating modes all the PWM1A, PWM1B, PWM2A, PWM2B signals are at the low logic value.

In the buck mode of operation the PWM1A signal is 180 degrees out of phase with the PWM1B signal and the PWM2A signal is 180 degrees out of phase with the PWM2B signal, as shown in Figure 6A.

Furthermore, in the buck operating mode the PWM1A signal is out of phase by a certain angle between 0 and 180 degrees with respect to the PWM2A signal, as shown in Figure 6A; in other words, the signals PWM1A and PWM2A are active simultaneously for a time interval which is comprised between 0 and maximum half of the switching period.

Similarly, in the buck operating mode the PWM1B signal is out of phase by a certain angle between 0 and 180 degrees with respect to the PWM2B signal, as shown in Figures 6A; in other words, the signals PWM1B and PWM2B are active simultaneously for a time interval which is comprised between 0 and half of the switching period.

Still in the buck mode, the control signals SINC2, SINC1 respectively of the switches S5, S6 are generated synchronously at the edges of the control signals PWM1A, PWM1B, PWM2A, PWM2B, as will be explained in more detail below.

The synchronous rectification circuit 11 is connected in parallel between the first terminal of the first inductor L1 and the first terminal of the second inductor L2.

In particular, the synchronous rectifying circuit 11 comprises two rectifying diodes DS5, DS6 which are connected in parallel to the switches S5, S6 respectively.

During the buck mode of operation, the rectifier diodes DS5, DS6 have the function of rectifying the secondary voltage Vsec generated at the ends of the secondary winding 10.2.

During the boost operating mode, on the other hand, the rectifier diodes DS5, DS6 are inversely polarized and therefore are equivalent to an open circuit.

The rectifier diode DS5 includes a cathode terminal connected to the terminal I of the switch S5, connected to the first terminal of the secondary winding 10.2 and connected to the first terminal of the first inductor L1; the rectifier diode DS5 comprises an anode terminal connected to the terminal O of the switch S5, connected to the anode of the rectifier diode DS6, connected to the switch S6, connected to the free-wheeling diode D3, connected to the capacitor C5 and connected to the fourth terminal d 'LV input / output.

The rectifier diode DS6 includes an anode terminal connected to the terminal I of the switch S6 and connected to the anode terminal of the rectifier diode DS5 (and therefore connected to the fourth input / output terminal LV-); the rectifier diode DS6 includes a cathode terminal connected to terminal O of the switch S6, connected to the second terminal of the secondary winding 10.2 and connected to the first terminal of the second inductor L2.

The switches S5, S6 are connected to each other in series and said series is placed in parallel with the secondary winding 10.2.

The switches S5, S6 include a respective control terminal C adapted to receive respectively a first and a second control signal SINC1, SINC2 to control the opening and closing respectively of the switches S5, S6.

The switches S5, S6 have the function, during each cycle of the boost operating mode, to switch between a closed and an open position according to the value of the control signals SINC2, SINC1, respectively, in order to transfer energy from the first inductor. L1 and from the second inductor L2 to the secondary winding 10.2, as will be explained in more detail below in relation to the description of Figure 5A.

In the buck operating mode, on the other hand, the switches S5, S6 switch between the open position and the closed position synchronously with respect to the switches S1, S2, S3, S4 of the full-bridge rectifier 5, as will be explained in more detail below. relative to the description of Figures 6A-6D.

The switches S5, S6 are made for example with MOSFET transistors or bipolar transistors.

In the boost-limit operating mode, the signals SINC2, SINC1, S_sf respectively control the switches S5, S6, S10 with periodic trends, as will be explained in more detail below in relation to the description of Figures 7A-7D.

Furthermore, the switches S5, S6 have the function, during each cycle of the buck operating mode, to switch between an open position and a closed position synchronously with respect to the four switches S1, S2, S3, S4, in order to connect / disconnect alternatively the first and second inductors L1, L2 to / from the low direct voltage level ∆LV, as will be explained in more detail below.

In particular, the switch S5 comprises a first terminal I connected to the first terminal (node N1) of the secondary winding 10.2 and to the first terminal (node N1) of the first inductor L1 and comprises a second terminal O connected to the switch S6, to the free-wheeling diode D3 and to the fourth input / output terminal LV-.

The switch S5 also includes a control terminal C adapted to receive a SINC2 signal which controls its opening and closing.

The rectifier diode DS5 is connected in parallel to the switch S5, i.e. the cathode terminal of the rectifier diode DS5 is connected to the first terminal I of the switch S5 and the anode terminal of the rectifier diode DS5 is connected to the second terminal O of the switch S5.

The switch S6 comprises a first terminal I connected to the second terminal O of the switch S5 (and therefore connected to the fourth input / output terminal LV- and to the free-wheeling diode D3) and comprises a second terminal O connected to the second terminal of the secondary winding 10.2 and to the first terminal (node N2) of the second inductor L2.

The switch S6 also includes a control terminal C adapted to receive a SINC1 signal which controls its opening and closing.

The rectifier diode DS6 is connected in parallel to the switch S6, i.e. the anode terminal of the rectifier diode DS6 is connected to the first terminal I of the switch S6 and the cathode terminal of the rectifier diode DS6 is connected to the second terminal O of the switch S6.

The output filter includes the first inductor L1, the second inductor L2 and the capacitor C5.

The first inductor L1 has the function, during the boost and boost-limit operating modes, to store energy and then to release the stored energy towards the secondary winding 10.2; on the other hand, in the buck mode of operation the first inductor L1 has the function (together with the capacitor C5) to perform a low-pass filtering.

The first inductor L1 includes a first terminal (node N1) connected to the first terminal of the secondary winding 10.2 and includes a second terminal connected to the second inductor L2; in addition, the second terminal of the first inductor L1 is connected to the cathode terminal of the recirculation diode D3 and to the throttling switch S10.

The second inductor L2 has the function, during the boost and boost-limit operating modes, of storing energy and then releasing the stored energy towards the secondary winding 10.2; on the other hand, in the buck operating mode, the second inductor L2 has the function (together with the capacitor C5) to perform a low-pass filtering.

The second inductor L2 comprises a first terminal (node N2) connected to the second terminal of the secondary winding 10.2 and includes a second terminal connected to the second terminal (node N3) of the second inductor L2; in addition, the second terminal of the second inductor L2 is connected to the cathode terminal of the recirculation diode D3 and to the throttling switch S10.

The set of switches S5, S6 and the output filter (including L1, L2, C5) creates a synchronous "current doubler".

The assembly of the recirculation diode D3 and of the capacity control switch S10 form a capacity control circuit which allows to limit, in the boost-limit operating mode in which the voltage difference between the HV + terminal and the HV- terminal is small ( for example, equal to 6 V), the value of the load current towards the high voltage generator 40 (and therefore allows to regulate the current on the high voltage load 45), as will be explained in more detail below in relation to the description of the Figures 7A-7D showing the operation of the DC-DC converter in the boost-limit mode.

This is achieved, in the boost-limit operating mode, with the recirculation diode D3 which works in counterphase to the throttling switch S10, namely:

- when the recirculation diode D3 conducts (or is directly polarized), the capacity control switch S10 is open;

- when the recirculation diode D3 does not conduct (or is reverse biased), the capacity control switch S10 is closed.

Therefore, the assembly of the free-wheeling diode D3 and the capacity switch S10 have the function of limiting the value of the current flowing in the low voltage side of the DC-DC converter 1, thus reducing the energy stored in the inductors L1 and L2 .

In the buck and boost operating modes, on the other hand, the recirculation diode D3 is reverse biased.

The recirculation diode D3 comprises a cathode terminal connected to the second terminal (node N3) of the first inductor L1; in addition, the cathode terminal of the recirculation diode D3 is connected to the second terminal of the first inductor L1, to the second terminal of the second inductor L2 and to the capacity switch S10.

The free-wheeling diode D3 comprises an anode terminal connected to the capacitor C5, to the fourth input / output terminal LV- and to the common node between the switches S5 and S6 (i.e. the anode terminal of the free-wheeling diode D3 is connected to the O of switch S5 and to terminal I of switch S6).

The throttling switch S10 includes a first terminal I connected to the second terminal (node N3) of the first inductor L1 and to the second terminal of the second inductor L2 (and therefore connected to the cathode terminal of the recirculation diode D3).

The capacity control switch S10 also includes a second terminal O connected to the capacitor C5 and to the third input / output terminal LV +.

The capacity switch S10 has the function, during the boost-limit operating mode, to periodically switch between an open position and a closed position in order to limit (in combination with the recirculation diode D3) the value of the current flowing. in the low voltage side of the DC-DC converter 1.

In the buck operating mode, on the other hand, the throttling switch S10 has an additional protection function, as it is such as to switch to the open position in order to disconnect the low voltage part of the DC-DC converter 1 from the low voltage battery. 41, in case of detection of a component failure in the low-voltage part of the DC-DC converter 1 (for example, a breaker failure or an internal short-circuit), thus avoiding the discharge of the low-voltage battery 41 .

The failure of a component in the low voltage part of the DC-DC converter 1 can be for example:

- a short circuit on the diode D3;

- a fault or a short circuit on switch S5 or S6;

- a fault or short-circuit on the rectifier diode DS5 or DS6.

In particular, said disconnection of the low voltage part of the DC-DC converter 1 occurs by electrically separating the third input / output terminal LV + from the node N3 common to the first and second inductors L1, L2.

The capacitor C5 is connected in parallel to the third and fourth input / output terminals LV +, LV-.

The capacitor C5 includes a first terminal connected to the capacity control switch S10 and to the third input / output terminal LV +.

The capacitor C5 also includes a second terminal connected to the terminal O of the switch S5, to the terminal I of the switch S6 and to the anode terminal of the recirculation diode D3.

The second terminal of the capacitor C5 is also connected to the fourth input / output terminal LV-; the DC low voltage level ∆LV therefore represents the voltage drop across capacitor C5.

The capacitor C5 in the buck operating mode has the function (together with the first or second inductor L1, L2) to perform a low-pass filtering.

In the boost and boost-limit operating modes, the capacitor C5 instead has the function of circulating the alternating component of the current flowing towards the inductors L1 and L2.

Preferably, the DC-DC converter 1 further comprises a protection diode D6 connected in parallel to the capacity control switch S10.

In particular, the protection diode D6 includes an anode terminal connected to the first terminal I of the throttling switch S10 and includes a cathode terminal connected to the second terminal O of the throttling switch S10.

Therefore the anode terminal of the protection diode D6 is connected to the second terminal (node N3) of the first inductor L1 and to the second terminal of the second inductor L2 and is connected to the cathode terminal of the recirculating diode D3.

The cathode terminal of the protection diode D6 is therefore connected to the first terminal of the capacitor C5 and to the third input / output terminal LV +.

The protection diode D6 has a safety function in the buck operating mode, in the event that the partialisation switch S10 (which in buck mode is always closed) should open in an uncontrolled manner (e.g. due to a fault): the diode D6 allows the outgoing currents from inductors L1 and L2 to flow towards the low voltage output ∆LV for the time necessary to detect the fault, avoiding overvoltages at node N3 on the low voltage side.

It should be noted that the diode D6 was shown as a separate element, but in the case where the throttling switch S10 is made with a MOSFET transistor, the diode D6 can be the body diode of the same MOSFET transistor S10.

Preferably, the high voltage portion of the DC-DC converter 1 further comprises a pair of cut-off diodes D1, D2, respectively connected between the first input / output terminal HV + and the resonance inductor L_res and between the inductor of resonance L_res and the second HV- input / output terminal.

The cut-off diodes D1, D2 have the function, in the buck, boost and boost-limit operating modes, to provide a low impedance path between their common node and the continuous high voltage level ∆HV, bypassing the high path. impedance provided by the resonance inductor L_res.

Specifically, the cathode terminal of the cutting diode D2 is connected to the first input / output terminal HV +, the anode terminal of the cutting diode D1 is connected to the second input / output terminal HV-, the cathode terminal of the cut-off diode D1 is connected to the second terminal of the resonance inductor L_res and also the anode terminal of the cut-off diode D2 is connected to the second terminal of the resonance inductor L_res (therefore the node common to the cut-off diodes D1 and D2 is connected to the second terminal of the resonance inductor L_res).

With reference to Figure 2A, a DC-DC converter 101 is shown based on a second embodiment of the invention.

The converter 101 of Figure 2A differs from that of Figure 1 in that it comprises a further cutting circuit 12 which includes:

- a cut-off diode D4;

- a cut-off diode D5;

- a resistor R2;

- a capacitor C1;

- a first damping resistor R1_dmp.

In the buck, boost and boost-limit operating mode, the cutting circuit 12 has the function of limiting the value of overvoltages in the low voltage side of the DC-DC converter 1, in particular limiting overvoltages on node N1 (by means of the cut D4 and capacitor C1) and on node N2 (by means of cut-off diode D5 and capacitor C1), constraining the voltage on node N1 and node N2 not to exceed the voltage of capacitor C1, thus limiting overvoltages in the circuit rectification 11 comprising the rectifying diodes DS5, DS6.

The cutting diode D4 includes an anode terminal connected to the first terminal of the secondary winding 10.2 (node N1); in addition, the anode terminal of the cutting diode D4 is connected to the first terminal of the first inductor L1, to the switch S5 and to the rectifier diode DS5.

The cut-off diode D4 comprises a cathode terminal connected to the resistor R2, the capacitor C1 and the cut-off diode D5.

The cut-off diode D5 comprises a cathode terminal connected to the cathode terminal of the cut-off diode D4; moreover, the cathode terminal of the cutting diode D5 is connected to the resistor R2 and to the capacitor C1.

The cutting diode D5 includes an anode terminal connected to the second terminal (node N2) of the secondary winding 10.2; in addition, the anode terminal of the cutting diode D5 is connected to the first terminal of the second inductor L2, to the switch S6 and to the rectifier diode DS6.

The resistor R2 comprises a first terminal connected to the cathode terminal of the cutting diode D4 and to the cathode terminal of the cutting diode D5 and comprises a second terminal connected to the node common to the first and second inductors L1, L2 (i.e. the second terminal of the Resistor R3 is connected to the second terminal of the first inductor L1 (node N3) and to the second terminal of the second inductor L2.

The capacitor C1 is connected in series to the first damping resistor R1_dmp and said series connection is interposed between the common node between the cutting diodes D4, D5 and the anode terminal of the recirculating diode D3.

In particular, the capacitor C1 comprises a first terminal connected to the cathode terminals of the cutting diodes D4, D5 and comprises a second terminal connected to the first damping resistor R1_dmp.

The first damping resistor R1_dmp comprises a first terminal connected to the second terminal of the capacitor C1 and comprises a second terminal connected to the anode terminal of the free-wheeling diode D3 and to the second terminal of the capacitor C5 (and therefore the second terminal of the first damping resistor R1_dmp is connected to the fourth input / output terminal LV-).

Diodes D4 and D5 bind the voltage respectively to node N1 and node N2 not to exceed the voltage of capacitor C1.

Resistor R2 forms a low-pass filter together with capacitor C1, so that the voltage on the latter tends to that on node N3.

The damping resistor R1_dmp operates a damping during the transients of the capacitor C1.

With reference to Figure 2B, a DC-DC converter 102 is shown based on a variant of the second embodiment of the invention.

The DC-DC converter 102 of Figure 2B differs from the DC-DC converter 101 of Figure 2A in that the second terminal of the resistor R2 is connected to the common node between the switches S5, S6.

With reference to Figure 3A, a DC-DC converter 101 according to a third embodiment of the invention is shown.

The converter 151 of Figure 3A differs from that of Figure 2A in that the cutting circuit further comprises:

- an S7 switch;

- an S8 switch,

- an S9 switch;

- a second damping resistor R2_dmp.

The switches S7, S8 are connected to each other in series and said series connection is placed in parallel to the secondary winding 10.2.

In the buck, boost and boost-limit operating mode, the S7, S8 switches switch between the open position and the closed position, in order to perform a synchronous cutting action, bypassing the asynchronous cut made by D4 and D5, in order to achieve lower power dissipation and improve the overall efficiency of the DC-DC converter 151.

The switch S7 is connected in parallel to the cutting diode D4 and includes a first terminal I connected to the anode terminal of the cutting diode D4 and a second terminal O connected to the cathode terminal of the cutting diode D4.

In addition, the first terminal I of the S7 switch is connected to the first terminal of the secondary winding 10.2, to the first terminal of the first inductor L1, to the switch S5 and to the rectifier diode DS5.

The second terminal O of the S7 switch is also connected to the first terminal of the resistor R2 and to the first terminal of the capacitor C1.

The S7 switch also includes a control terminal C adapted to receive a control signal SC2 which controls its periodic opening and closing.

The switch S8 is connected in parallel to the cutting diode D5 and includes a first terminal I connected to the cathode terminal of the cutting diode D5 and a second terminal O connected to the anode terminal of the cutting diode D5.

Furthermore, the first terminal I of the switch S8 is connected to the terminal O of the switch S7, to the first terminal of the resistor R2 and to the first terminal of the capacitor C1.

The second terminal O of the switch S9 is also connected to the second terminal of the secondary winding 10.2, to the first terminal of the second inductor L2, to the switch S6 and to the rectifier diode DS6.

The switch S8 also includes a control terminal C adapted to receive a control signal SC1 which controls its periodic opening and closing.

The second damping resistor R2_dmp and switch S9 are connected in series and said series connection is placed in parallel with the first damping resistor R1_dmp.

Circuit-breakers S7 and S8 operate in push-pull respectively to circuit-breakers S5 and S6, that is, with the exception of the short dead time to allow switching:

- when the S7 switch is open, the S5 switch is closed, while when the S7 switch is closed, the S5 switch is open;

- when switch S8 is open, switch S6 is closed, while when switch S8 is closed, switch S6 is open.

The damping resistor R2_dmp is connected in parallel to the damping resistor R1_dmp by closing the switch S9, going to modify the overall damping resistance, in order to optimize the operation of the cutting circuit 12 in the boost, buck and boost operating modes. limit.

Figures 5A-5D show a possible trend in a cycle of duration ∆Tb (equal for example to 10 us) of some signals generated in the DC-DC converter 151 of Figures 3A-3B which operates in the boost mode and in the system of Figure 4 ; the signals are repeated periodically in successive cycles.

The signals shown in Figures 5A-5D have the following meanings: - SINC1 (S6): control signal of switch S6;

- SC1 (S8): S8 switch control signal;

- SINC2 (S5): S5 switch control signal;

- SC2 (S7): control signal of the S7 switch;

- I (S10): current flowing through the capacity control switch S10;

- I (D4): current flowing through the cutting diode D4;

- I (D5): current flowing through the cutting diode D5;

- I (L1): current flowing through the first inductor L1;

- I (L2): current flowing through the second inductor L2;

- Isec: current flowing through the secondary winding 10.2; - Vsec: voltage across the secondary winding 10.2;

- Vpr: voltage across the primary winding 10.1;

- I (D1): current flowing through the cut-off diode D1;

- I (D2): current flowing through the cut-off diode D2;

- I (DS2): current flowing through the diode DS2;

- I (DS3): current flowing through the diode DS3.

In Figure 5A It is considered that the control signals of the switches have a low logic value (V_L) which opens the switch and a high logic value (V_H) which closes the switch.

Figures 6A-6D show a possible trend in a cycle of duration ∆Tk (equal for example to 10 us) of some signals generated in the DC-DC converter 151 of Figures 3A-3B which operates in the buck mode and in the system of Figure 4 ; the signals are repeated periodically in successive cycles.

In Figure 6A and 6C it is considered that the control signals of the switches have a low logic value (V_L) which opens the switch and a high logic value (V_H) which closes the switch.

The signals shown in Figures 6A-6D have the following meanings: - PWM2A (S2): control signal of switch S2;

- PWM2B (S3): S3 switch control signal;

- PWM1B (S4): S4 switch control signal;

- PWM1A (S1): switch S1 control signal;

- Vpr: voltage across the primary winding 10.1;

- Ipr: current flowing through the primary winding 10.1; - I (L1): current flowing through the first inductor L1;

- I (L2): current flowing through the second inductor L2;

- SINC1 (S6): control signal of switch S6;

- SC1 (S8): S8 switch control signal;

- SINC2 (S5): S5 switch control signal;

- SC2 (S7): control signal of the S7 switch;

- I (D4): current flowing through the cutting diode D4;

- I (D5): current flowing through the cutting diode D5;

- I (DS5): current flowing through the rectifier diode DS5; - I (DS6): current flowing through the rectifier diode DS6; - I (S5): current flowing through the switch S5;

- I (S6): current flowing through the switch S6;

- I (S7): current flowing through the S7 switch;

- I (S8): current flowing through the switch S8;

- V (N1): voltage of node N1 (equal to the voltage drop across the switch S5);

- V (N2): voltage of node N2 (equal to the voltage drop across the switch S6);

It is possible to observe in Figure 6A and 6C that switches S1, S2, S3, S4 are synchronous with respect to switches S5, S6.

Figures 7A-7D show a possible trend in a cycle of duration ∆Tl (equal for example to 10 us) of some signals generated in the DC-DC converter 151 of Figures 3A-3B which operates in the boost-limit mode and in the Figure 4; the signals are repeated periodically in successive cycles.

The signals shown in Figures 7A-7D have the following meanings: - SINC1 (S6): control signal of the switch S6;

- SC1 (S8): S8 switch control signal;

- SINC2 (S5): S5 switch control signal;

- SC2 (S7): control signal of the S7 switch;

- S_sf (S10): control signal of the capacity control switch S10;

- I (D3): current flowing through the recirculation diode D3;

- I (S10): current flowing through the capacity control switch S10;

- I (D4): current flowing through the cutting diode D4;

- I (D5): current flowing through the cutting diode D5;

- I (L1): current flowing through the first inductor L1;

- I (L2): current flowing through the second inductor L2;

- V (N3): voltage of node N3 (node common to the first and second inductors L1, L2), measured with respect to the LV- terminal;

- Isec: current flowing through the secondary winding 10.2; - Vsec: voltage across the secondary winding 10.2;

- Vpr: voltage across the primary winding 10.1;

- I (D1): current flowing through the cut-off diode D1;

- I (D2): current flowing through the cut-off diode D2;

- I (DS2): current flowing through the diode DS2;

- I (DS3): current flowing through the diode DS3.

In Figure 7A it is considered that the control signals of the switches have a low logic value (V_L) which opens the switch and a high logic value (V_H) which closes the switch.

It is possible to observe in Figure 7B that the recirculation diode D3 works in counterphase to the partialisation switch S10 and this allows to limit the value of the current flowing in the low voltage side of the DC-DC converter 1 (thus reducing the energy stored in the inductors L1 and L2), even if the voltage difference between the HV + terminal and the HV- terminal is small (for example, equal to 6 V).

In particular, for each operating cycle of the boostlimit mode it is possible to observe:

- during a first time interval ∆T1l and during a second time interval ∆T2l (subsequent to ∆T1l), the recirculation diode D3 is directly polarized, while the capacity control switch S10 is open;

- during a third time interval ∆T3l (subsequent to ∆T2l) the recirculation diode D3 is reverse biased, while the capacity control switch S10 is closed;

- during a fourth time interval ∆T4l (subsequent to ∆T3l) and during a fifth time interval ∆T5l (subsequent to ∆T4l), the recirculation diode D3 is directly polarized, while the throttling switch S10 is open;

- during a sixth time interval ∆T6l (subsequent to ∆T5l) the recirculation diode D3 is reverse biased, while the capacity control switch S10 is closed.

It is also possible to observe in Figure 7D that the first cutting diode D1 works in counterphase to the second cutting diode D2 and this allows to provide a low impedance path between their common node and the high continuous voltage level ∆HV, bypassing the high impedance path provided by the resonance inductor L_res.

In particular:

- during the first time interval ∆T1 and during a first portion of the second time interval ∆T2l, the first cut-off diode D1 is in the state of reverse bias, while the second cut-off diode D2 is in the state of forward bias;

- during a second portion of the second time interval ∆T2l, during the third time interval ∆T3l and during a first portion of a fourth time interval ∆T4l, the first cut-off diode D1 is in the forward bias state, while the second cut-off diode D2 is in the reverse bias state;

- during a second portion of the fourth time interval ∆T4l, during the fifth time interval ∆T5l and during the sixth time interval ∆T6l, the first cut-off diode D1 is in the reverse bias state, while the second cut-off diode D2 is in the state of forward polarization.

With reference to Figure 3B, a DC-DC converter 152 is shown based on a variant of the third embodiment of the invention.

The DC-DC converter 152 of Figure 3B differs from the DC-DC converter 151 of Figure 3A in that the second terminal of the resistor R2 is connected to the common node between the switches S5, S6.

Figure 4 shows a power supply and control system 50 which includes:

- a DC-DC converter of the type, alternatively, 1, 101, 102, 151, 152 of the embodiments illustrated above;

- a driving device 30;

- a high voltage battery 40 connected in parallel to the high voltage side (i.e. connected to the first and second input / output terminals HV +, HV-);

- a high voltage load 45 connected to the high voltage battery 40;

- a low voltage battery 41 connected in parallel to the low voltage side (i.e. connected to the third and fourth input / output terminals LV +, LV-);

- a low voltage load 46 connected to the low voltage battery 41.

The high-voltage load 45 is for example an electric motor of a vehicle with electric propulsion or a mixed electric-internal combustion engine (i.e. of a hybrid vehicle), while the low-voltage load 46 is for example constituted by the electrical services in the passenger compartment of the same vehicle.

The driving device 30 has the function of suitably generating the values of the logic signals PWM1A, PWM1B, PWM2A, PWM2B, SINC2, SINC1, SC2, SC1, S_md, S_sf to control switches S1, S4, S2, S3, S5, respectively, S6, S7, S8, S9, S10.

In particular:

- in the buck operating mode, the driving device 30 generates the periodic variable signals PWM1A, PWM1B, PWM2A, PWM2B, SINC2, SINC1, SC2, SC1 and generates the constant signals S_md, S_sf;

- in the boost operating mode, the driving device 30 generates the periodic variable signals SINC2, SINC1, SC2, SC1 and generates the constant signals PWM1A, PWM1B, PWM2A, PWM2B, S_md, S_sf;

- in the boost-limit operating mode, the driving device 30 generates the periodic variable signals SINC2, SINC1, SC2, SC1, S_sf and generates the constant signals PWM1A, PWM1B, PWM2A, PWM2B, S_md.

The operation of the DC-DC converter 151 of Figure 3A in the buck operation mode will now be described, also referring to Figures 1, 2A, 3A, 4 and 6A-6D.

Figures 6A-6D show a period ∆Tk comprising the following eight successive time intervals ∆T1k, ∆T2k, ∆T3k, ∆T4k, ∆T5k, ∆T6k, ∆T7k, ∆T8k, in which:

- during the first time interval ∆T1k (between the initial instant t21 and the instant t23) the switches S2, S4 are closed, the switches S3, S1 are open, the primary voltage Vpr across the primary winding 10.1 is greater than zero, the primary current Ipr has an increasing trend in order to load energy in the primary winding 10.1, the signal SC2 has a low logic value which opens the switch S7, the cut-off diode D4 is inversely biased, the signal SC1 has low logic value which keeps switch S8 open, D5 cut-off diode is reverse biased, SINC2 signal has low logic value which keeps switch S5 open, DS5 rectifier diode is reverse biased, SINC1 signal has a high logic value which keeps the switch S6 closed, the rectifier diode DS6 is reverse biased, the S_md signal has a low logic value which keeps the S9 switch open, the S_sf signal has a value high logic that keeps the throttling switch S10 closed, the assembly of the first inductor L1, second inductor L2, capacitor C5 performs a low-pass filtering, then a current flow is generated that flows towards the output terminal LV + through the inductors L1 and L2 and the switch S10;

- during the second time interval ∆T2k (between the instant t23 and the instant t24), the switches S2, S1 are closed, the switches S3, S4 are open, the primary voltage Vpr across the primary winding 10.1 has a value substantially equal to zero, the primary current Ipr has a decreasing trend with positive values, the signal SC2 has a low logic value which keeps the switch S7 open, the cut-off diode D4 is inversely biased, the signal SC1 has a low logic value that keeps the switch S8 open, the cut-off diode D5 is reverse biased, the signal SINC2 switches to a high logic value which closes the switch S5, the rectifier diode DS5 is reverse biased, the signal SINC1 has a value high logic that keeps the switch S6 closed, the rectifier diode DS6 is reverse biased, the S_md signal has a low logic value that keeps the S9 switch open, the S_sf signal has an alt logic value or which keeps the partialisation switch S10 closed, the assembly of the first inductor L1, second inductor L2, capacitor C5 performs a low-pass filtering, therefore a current flow is generated which flows towards the output terminal LV + through the inductors L1 and L2 and the capacity switch S10;

- during the third time interval ∆T3k (between the instant t24 and the instant t28) the switches S3, S1 are closed, the switches S2, S4 are open, the primary voltage Vpr across the primary winding 10.1 has a decreasing trend in steps with values less than zero, the primary current Ipr has a decreasing trend from positive to negative values, the signal SC2 has a low logic value which keeps the switch S7 open, the cut-off diode D4 is inversely biased, the signal SC1 has a low logic value which keeps the switch S8 open, the cut-off diode D5 between the instants t24 and t26 (t26 excluded) is inversely biased, then at the instant t26 the cut-off diode D5 switches to direct bias to the in order to limit the voltage on node N2 and after at instant t27 the cut-off diode D5 switches back to reverse bias, the signal SINC2 has a high logic value which keeps the switch S5 closed, the rectifier diode DS5 is pole inversely, the signal SINC1 switches to a low logic value which opens the switch S6, the rectifier diode DS6 switches to forward bias at instant t24 and then to reverse bias at instant t25, the signal S_md has a low logic value which keeps the switch S9 open, the signal S_sf has a high logic value which keeps the partialisation switch S10 closed, the assembly of the first inductor L1, second inductor L2, capacitor C5 performs a low-pass filtering, therefore a current flow that flows towards the output terminal LV + through the inductors L1 and L2 and the capacity switch S10;

- during the fourth time interval ∆T4k (between the instant t28 and the instant t29) the switches S3, S1 are closed, the switches S2, S4 are open, the cut-off diodes D2, D1 are inversely polarized, the primary voltage Vpr across the primary winding 10.1 is less than zero, the primary current Ipr has a decreasing trend with negative values, the signal SC2 has a low logic value which keeps the switch S7 open, the cut-off diode D4 is polarized inversely, the signal SC1 has a high logic value which keeps the switch S8 closed, the cut-off diode D5 is reverse biased, the signal SINC2 has a high logic value which keeps the switch S5 closed, the rectifier diode DS5 is reverse biased , the signal SINC1 switches to a low logic value which opens the switch S6, the rectifier diode DS6 is reverse biased, the signal S_md has a low logic value which keeps the switch S9 open, the signal S_ sf has a high logic value that keeps the throttling switch S10 closed, the assembly of the first inductor L1, second inductor L2, capacitor C5 performs a low-pass filtering, therefore a current flow is generated towards the output terminal LV + which flows through the inductors L1 and L2 and the capacity switch S10;

- during the fifth time interval ∆T5k (between the instant t29 and the instant t30) the switches S2, S4 are open, the switches S3, S1 are closed, the primary voltage Vpr across the primary winding 10.1 is less than zero, the primary current Ipr has a decreasing trend in order to load energy in the primary winding 10.1, the signal SC2 has a low logic value which opens the switch S7, the cut-off diode D4 is inversely biased, the signal SC1 has a low logic value which keeps the switch S8 open, the cut-off diode D5 is reverse biased, the signal SINC2 has a high logic value which keeps the switch S5 closed, the rectifier diode DS5 is reverse biased, the signal SINC1 has a low logic value that keeps the switch S6 open, the rectifier diode DS6 is reverse biased, the signal S_md has a low logic value which keeps the switch S9 open, the signal S_sf has a logic value which keeps the partialisation switch S10 closed, the assembly of the first inductor L1, second inductor L2, capacitor C5 performs a low-pass filtering, then a current flow is generated which flows towards the output terminal LV + through the inductors L1 and L2 and the capacity switch S10.

- during the sixth time interval ∆T6k (between the instant t30 and the instant t32), the switches S2, S1 are open, the switches S3, S4 are closed, the primary voltage Vpr across the primary winding 10.1 has a value substantially equal to zero, the primary current Ipr has an increasing trend with negative values, the signal SC2 has a low logic value which keeps the switch S7 open, the cut-off diode D4 is inversely biased, the signal SC1 has a low logic value that keeps switch S8 open, cut-off diode D5 is reverse biased, signal SINC2 has a high logic value that keeps switch S5 closed, rectifier diode DS5 is reverse biased, signal SINC1 switches to a high logic value that closes the switch S6, the rectifier diode DS6 is reverse biased, the signal S_md has a low logic value which keeps the switch S9 open, the signal S_sf has a high logic value ch and keeps the throttling switch S10 closed, the assembly of the first inductor L1, second inductor L2, capacitor C5 performs a low-pass filtering, then a current flow is generated which flows towards the output LV + through the inductors L1 and L2 and the capacity switch S10;

- during the seventh time interval ∆T7k (between the instant t32 and the instant t40) the switches S3, S1 are open, the switches S2, S4 are closed, the primary voltage Vpr across the primary winding 10.1 has an increasing trend in steps with values greater than zero, the primary current Ipr has a decreasing trend from negative to positive values, the signal SC2 has a low logic value which keeps the switch S7 open, the cut-off diode D5 is inversely biased, the signal SC1 has a low logic value which keeps the switch S8 open, the cut-off diode D4 between the instants t32 and t34 (t34 excluded) is inversely biased, then at the instant t34 the cut-off diode D4 switches to forward bias to in order to limit the voltage on node N3 and after at instant t35 the cut-off diode D4 switches back to reverse bias, the signal SINC2 switches to a low logic value which opens the switch S5, the rectifier diode DS6 is pole inversely, the signal SINC1 has a high logic value which keeps the switch S6 closed, the rectifier diode DS5 switches to forward bias at instant t32 and then to reverse bias at instant t33, the signal S_md has a low logic value that keeps the switch S9 open, the signal S_sf has a high logic value which keeps the partialisation switch S10 closed, the assembly of the first inductor L1, second inductor L2, capacitor C5 performs a low-pass filtering, therefore a current flow that flows towards the output terminal LV + through the inductors L1 and L2 and the capacity switch S10;

- during the eighth time interval ∆T8k (between the instant t40 and the instant t42) the switches S3, S1 are open, the switches S2, S4 are closed, the cut-off diodes D2, D1 are inversely polarized, the primary voltage Vpr across the primary winding 10.1 is greater than zero, the primary current Ipr has an increasing trend with positive values, the signal SC2 has a high logic value which keeps the switch S7 closed, the cut-off diode D4 is reverse biased, the SC1 signal has a low logic value which keeps the S8 switch open, the D5 cut-off diode is reverse biased, the SINC2 signal switches to a low logic value which opens the S5 switch, the DS5 rectifier diode is biased inversely, the SINC1 signal has a high logic value which keeps the S6 switch closed, the DS6 rectifier diode is reverse biased, the S_md signal has a low logic value which keeps the S9 switch open, the S_s signal f has a high logic value that keeps the throttling switch S10 closed, the assembly of the first inductor L1, second inductor L2, capacitor C5 performs a low-pass filtering, therefore a current flow is generated towards the output terminal LV + flowing through the inductors L1 and L2 and the capacity switch S10.

The operation of the DC-DC converter 151 of Figure 3A in the boost operation mode will now be described, also referring to Figures 1, 4 and 5A-5D.

Figures 5A-5D show a period ∆Tb comprising the following four successive time intervals ∆T1b, ∆T2b, ∆T3b, ∆T4b, in which:

- during the first time interval ∆T1b (between the initial instant t1 and the instant t3) the control signal SINC2 has a high logic value which closes the switch S5, the control signal SINC1 switches to a logic value high that closes the switch S6, current flows with increasing trend through the first inductor L1 which charges, current flows with increasing trend through the second inductor L2 which charges, the secondary voltage Vsec across the secondary winding 10.2 is zero, the secondary current Isec through the secondary winding 10.2 has a negative value;

- during the second time interval ∆T2b (between the instant t3 and the instant t5) the control signal SINC2 switches to a low logic value which opens the switch S5, the control signal SINC1 has a high logic value which keeps the switch S6 closed, current flows with decreasing trend through the first inductor L1 which discharges, current flows with increasing trend through the second inductor L2 which charges, the secondary voltage Vsec across the secondary winding 10.2 has a pulse positive and then stabilizes at the positive value ∆HV divided by the transformation ratio, the current through the first inductor L1 flows through the secondary winding 10.2 of the transformer 10 and energy is then transferred from the secondary winding 10.2 to the primary winding 10.1, i diodes D1 and DS2 are directly biased and rectify the primary voltage Vpr, while diodes D2 and DS3 are biased inversely;

- during the third time interval ∆T3b (between the instant t5 and the instant t7) the control signal SINC2 has a high logic value which closes the switch S5, the control signal SINC1 has a high logic value which the switch S6 closes, current flows with increasing trend through the first inductor L1 which charges, current flows with increasing trend through the second inductor L2 which charges, the secondary voltage Vsec across the secondary winding 10.2 is zero, the current secondary Isec through the secondary winding 10.2 has a positive value;

- during the fourth time interval ∆T4b (between the instant t7 and the instant t10) the control signal SINC2 has a high logic value which closes the switch S5, the control signal SINC1 has a low logic value which opens the switch S6, current flows with increasing trend through the first inductor L1 which charges, current flows with decreasing trend through the second inductor L2 which discharges, the secondary voltage Vsec across the secondary winding 10.2 has a negative pulse for then stabilize at the negative value -∆HV divided by the transformation ratio, the current through the second inductor L2 flows through the secondary winding 10.2 of the transformer 10 and then energy is transferred from the secondary winding 10.2 to the primary winding 10.1, the diodes D2 and DS3 are directly biased and rectify the primary voltage Vpr, while diodes D1 and DS2 are inversely biased;

The operation of the DC-DC converter 151 of Figure 3A in the boost-limit operation mode will now be described, also referring to Figures 1, 2A, 3A, 4 and 7A-7D.

Figures 7A-7D show a period ∆Tb comprising the following six successive time intervals ∆T1l, ∆T2l, ∆T3l, ∆T4l, ∆T5l, ∆T6l, in which: - during the first time interval ∆T1l (including between the initial instant t50 and the instant t52) the control signal SINC2 has a high logic value which keeps the switch S5 closed, the control signal SINC1 has a low logic value which keeps the switch S6 open, the signal control S_sf has a low logic value which opens the partialisation switch S10, the current flowing through the first inductor L1 recirculates through the closed switch S5 and the recirculation diode D3 directly biased, while the current through the second inductor L2 flows through the secondary winding 10.2 of the transformer 10 transferring energy from the secondary winding 10.2 to the primary winding 10.1, the secondary voltage Vsec across the secondary winding 10.2 is equal to the voltage -∆HV divided for the transformation ratio N, the diodes D1, DS2 are reverse biased, the diodes D2, DS3 are directly biased;

- during the second time interval ∆T2l (between the instant t52 and the instant t54) the control signal SINC2 has a transition from a high logic value to a low logic value which opens the switch S5, the control SINC1 has a transition from a low logic value to a high logic value which closes the switch S6, the control signal S_sf has a low logic value which keeps the capacity switch S10 open, the current flowing through the second inductor L2 recirculates through the closed switch S6 and the diode D3 directly biased, while the current through the first inductor L1 flows through the secondary winding 10.2 of the transformer 10, transferring energy from the secondary winding 10.2 to the primary winding 10.1, the secondary voltage Vsec at the ends of the secondary winding 10.2 has a positive pulse and then settles at the voltage ∆HV divided by the transformation ratio N, the current secondary Isec through the secondary winding 10.2 becomes positive, the primary voltage Vpr across the primary winding 10.1 becomes equal to ∆HV after a short dead time, the diodes D1 and DS2 switch to the state of forward bias after a short dead time and they carry out the rectification of the primary voltage Vpr, while the diodes DS3 and D2 switch to the state of reverse bias after a short dead time;

- during the third time interval ∆T3l (between the instant t54 and the instant t56) the control signal SINC2 has a low logic value which keeps the switch S5 open, the control signal SINC1 has a high logic value which keeps the switch S6 closed, the control signal S_sf has a transition from the low logic value to a high logic value which closes the capacity switch S10, current flows with increasing trend through the second inductor L2 which is charged by means of a current flowing from the third terminal LV + to the fourth terminal LV - passing through the capacity switch S10, the second inductor L2 and the switch S6, the recirculation diode D3 switches from the state of forward to reverse bias, the secondary voltage Vsec at the ends of the secondary winding 10.2 maintains the constant value, the secondary current Isec is positive, the primary voltage Vpr at the ends of the primary winding 10.2 is constant te and positive, the diodes D2, DS3 are reverse biased, the diodes D1, DS2 are directly biased;

- during the fourth time interval ∆T4l (between the instant t56 and the instant t58) the control signal SINC2 has a low logic value which keeps the switch S5 open, the control signal SINC1 has a high logic value which keeps the switch S6 closed, the control signal S_sf has a transition from the high logic value to the low logic value which opens the capacity switch S10, the current flowing through the second inductor L2 recirculates through the closed switch S6 and the recirculation diode D3 directly biased, while the current through the first inductor L1 flows through the secondary winding 10.2 of the transformer 10, transferring energy from the secondary winding 10.2 to the primary winding 10.1, the secondary voltage Vsec across the secondary winding 10.2 remains positive, the primary voltage Vpr across the primary winding 10.1 is also positive and constant, the diodes D2, DS3 are poles inverted, the diodes D1, DS2 are directly biased;

- during the fifth time interval ∆T5l (between the instant t58 and the instant t60), the control signal SINC2 has a transition from a low logic value to a high logic value which closes the switch S5, the signal control signal SINC1 has a transition from a high logic value to a low logic value which opens the switch S6, the control signal S_sf has a low logic value which keeps the capacity switch S10 open, the current in the first inductor L1 recirculates through the closed switch S5 and the recirculation diode D3, while the current through the second inductor L2 flows through the secondary winding 10.2 of the transformer 10, transferring energy to the primary winding 10.1, the secondary voltage Vsec across the secondary winding 10.2 has a negative pulse and then settles at the voltage -∆HV divided by the transformation ratio, the secondary current Isec through the secondary winding 10.2 becomes n egative, the primary voltage Vpr across the primary winding 10.2 becomes equal to -∆HV after a short dead time, the diodes DS3 and D2 switch to the state of forward bias after a short dead time and rectify the primary voltage Vpr, diodes D1 and DS2 switch to the reverse bias state after a short dead time;

- during the sixth time interval ∆T6l (between the instant t60 and the instant t62), the control signal SINC2 has a high logic value which keeps the switch S5 closed, the control signal SINC1 has a logic value low which keeps the switch S6 open, the control signal S_sf has a transition from a low logic value to a high logic value which closes the partialisation switch S10, current flows with increasing trend through the first inductor L1 which charges for by means of a current flowing from the third terminal LV + towards the fourth terminal LV- crossing the capacity switch S10, the first inductor L1 and the switch S5, the recirculation diode D3 switches from the state of forward to reverse bias, the voltage secondary Vsec at the ends of the secondary winding 10.2 remains negative and constant, the secondary current Isec is negative, the primary voltage Vpr at the ends of the primary winding 10.2 yes but It contains negative and constant, diodes D1, DS2 are reverse biased, diodes D2, DS3 are directly biased.

It should be noted that in the boost-limit operating mode the diodes DS1, DS4 and switches S1, S4 substantially do not participate in the continuous-continuous conversion due to the high impedance presented by the resonance inductor L_res.

Claims (10)

CLAIMS 1. DC-DC converter (1; 151) comprising: - a rectifier (5; DS1, DS2, DS3, DS4) adapted to generate a first level of direct voltage (∆HV); - a transformer (10) comprising a primary winding (10.1) connected to the rectifier and comprising a secondary winding (10.2), having a defined voltage transformation ratio; - a resonance inductor (L_res) interposed between the rectifier and the primary winding (10.1); - a first (S5) and a second (S6) switch connected to each other in series, said series being placed in parallel with the secondary winding, in which the first and the second switch comprise a respective control terminal adapted to receive a first (SINC2) and a second (SINC1) control signal for opening and closing respectively of the first and second circuit-breaker; - a first inductor (L1) having a first terminal connected to a first terminal of the secondary winding; - a second inductor (L2) having a first terminal connected to a second terminal of the secondary winding and having a second terminal connected to a second terminal of the first inductor; - a free-wheeling diode (D3) having a cathode terminal connected to the second terminal of the first inductor (L1) and having an anode terminal connected to a common node between the first and the second switch, in which the anode terminal of the diode of recirculation is adapted to receive a lower value (LV-) of a second level of direct voltage (∆LV); - a capacity switch (S10) having: • a first terminal (I) connected to the second terminal of the first and second inductor and further connected to the cathode terminal of the recirculating diode (D3); • a second terminal (O) adapted to receive a higher value (LV +) of the second direct voltage level (∆LV); • a control terminal (C) adapted to receive a third signal (S_sf) to control the opening and closing of the capacity switch; - an electronic driving device (30) capable of generating the first (SINC2), second (SINC1) and third (S_sf) control signals, the DC-DC converter being configured to operate in a first operating mode (t50, t62; ∆Tl) in which the input is the second voltage level (∆LV) and the output is the first voltage level (∆ HV); where free-wheeling diode (D3) is configured for: - operate in direct polarization (t50, t52, t56, t58), when the capacity switch (S10) is in an open position; - operate in reverse polarization (t54, t60), when the capacity switch (S10) is in a closed position. 2. DC-DC converter according to claim 1, further comprising: - a plurality of circuit-breakers (S1, S2, S3, S4) with bridge topology comprising a first (S1, S4) and a second (S2, S3) branch, the two branches being suitable for receiving the first direct voltage level ( ∆HV), in which said plurality of switches is configured to periodically switch between an open and a closed position as a function of the values of a corresponding plurality of control signals (PWM1A, PWM1B, PWM2A, PWM2B); - a rectification circuit (11; DS5, DS6) connected in parallel between the first terminal of the first inductor (L1) and the first terminal of the second inductor (L2); - a protection diode (D6) having the anode terminal connected to the first terminal (I) of the throttling switch (S10) and having the cathode terminal connected to the second terminal (O) of the throttling switch (S10); the DC-DC converter being further configured to operate in a second operating mode (t21, t42; ∆Tk) in which the input is the first direct voltage level (∆HV) and the output is the second voltage level DC (∆LV), where the second DC voltage level is less than the first DC voltage level, in which the electronic piloting device (30) is configured to generate the third control signal that closes the capacity control switch (S10) in the second operating mode, and in which the capacity control switch (S10) is further configured, in the second operating mode, to switch to the open position, in the event that a fault occurs in the first and / or second switch (S5, S6); and in which the protection diode (D6) is configured to switch to direct polarization, in the event of unwanted opening of the capacity switch (S10) in the second operating mode. 3. DC-DC converter according to any one of the preceding claims, further comprising a cutting circuit (D1, D2) comprising: - a first cut-off diode (D1) having the anode terminal adapted to receive a lower value (HV-) than the first direct voltage level (∆HV) and having the cathode terminal connected to a common node between the resonance (L_res) and the primary winding (10.1); - a second cut-off diode (D2) having the cathode terminal adapted to receive a higher value (HV +) of the first direct voltage level (∆HV) and having the anode terminal connected to the cathode terminal of the first cut-off diode ( D1); in which the first diode and the second diode are configured to switch, in the first operating mode, between reverse bias and forward bias, and in which: - when the first cut diode (D1) is in the forward bias state (t54, t56, t58), the second cut diode is in the reverse bias state; - when the second cut-off diode (D2) is in the forward bias state (t50, t52), the first cut-out diode is in the reverse bias state. 4. DC-DC converter according to any one of the preceding claims, comprising a further cut-off circuit (12) which includes: - a further first cut-off diode (D4) and a further second cut-off diode (D5) having the cathode terminals connected in common, in which the anode of the further first cut-off diode (D4) is connected to the first terminal of the secondary winding and to the first terminal of the first inductor (L1) and the anode of the further second cut-off diode ( D5) is connected to the second terminal of the secondary winding and to the first terminal of the second inductor (L2); - a resistor (R2) having a first terminal connected to the common cathode between the further first cut-off diode (D4) and the further second cut-off diode (D5) and having a second terminal connected to the node common to the first and second inductors (L1, L2); - a series connection of a capacitor (C1) and of a first damping resistor (R1_dmp), in which said series connection is interposed between the common cathode between the further first cutting diode (D4) and the further second diode cut-off (D5) and the lower value (LV-) of the second direct voltage level (∆LV). 5. DC-DC converter according to claim 4, wherein the further cutting circuit (12) further comprises a third switch (S7) and a fourth switch (S8) connected together in series, said series connection being placed in parallel to the secondary winding (10.2), the third and fourth circuit breakers comprising a respective control terminal adapted to receive a third (SC2) and a fourth (SC1) control signal for opening and closing respectively of the third and fourth circuit breaker, in which the further first cutting diode (D4) is connected in parallel to the third switch (S7) and the further second cutting diode (D5) is connected in parallel to the fourth switch (S8). 6. DC-DC converter according to claims 4 or 5, further comprising the series connection of a fifth switch (S9) and a second damping resistor (R2_dmp), in which said series connection is placed in parallel with the first damping (R1_dmp), in which the electronic driving device (30) is configured to generate a signal (S_md) for controlling the opening and closing of the fifth switch (S9). 7. DC-DC converter according to any one of the preceding claims, further comprising a capacitor (C5) having a first terminal connected to the second terminal of the throttling switch (S10) and having a second terminal connected to the anode terminal of the recirculating diode . 8. DC-DC converter according to any of the previous claims, in which the resonance inductor (L_res) is integrated into the transformer (10), being constituted by the dispersion inductance of the primary winding (10.1). 9. Power supply and control system (50) comprising: - a DC-DC converter (1, 101, 102, 151, 152) according to any one of the preceding claims; - a first battery (40) having a positive terminal adapted to receive the upper value (HV +) of the first direct voltage level (∆HV); - a second battery (41) having a positive terminal adapted to receive the upper value (LV +) of the second direct voltage level (∆LV); - a first electrical load (45) connected in parallel to the first battery (40); - a second electrical load (46) connected in parallel to the second battery (41). 10. Electric motor vehicle or hybrid motor of the electric / thermal type, comprising a power supply and control system according to claim 9.