IT7825515A0 - Procedimento per la fabbricazione di elementi semiconduttori. - Google Patents

Procedimento per la fabbricazione di elementi semiconduttori.

Info

Publication number
IT7825515A0
IT7825515A0 IT7825515A IT2551578A IT7825515A0 IT 7825515 A0 IT7825515 A0 IT 7825515A0 IT 7825515 A IT7825515 A IT 7825515A IT 2551578 A IT2551578 A IT 2551578A IT 7825515 A0 IT7825515 A0 IT 7825515A0
Authority
IT
Italy
Prior art keywords
procedure
manufacture
semiconductor elements
semiconductor
elements
Prior art date
Application number
IT7825515A
Other languages
English (en)
Other versions
IT1098670B (it
Original Assignee
Semikron Gleichrichterbau
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semikron Gleichrichterbau filed Critical Semikron Gleichrichterbau
Publication of IT7825515A0 publication Critical patent/IT7825515A0/it
Application granted granted Critical
Publication of IT1098670B publication Critical patent/IT1098670B/it

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Weting (AREA)
  • Die Bonding (AREA)
  • Formation Of Insulating Films (AREA)
  • Dicing (AREA)
IT25515/78A 1977-07-11 1978-07-10 Procedimento per la fabbricazione di elementi semiconduttori IT1098670B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19772731221 DE2731221A1 (de) 1977-07-11 1977-07-11 Verfahren zum herstellen von halbleiterkoerpern

Publications (2)

Publication Number Publication Date
IT7825515A0 true IT7825515A0 (it) 1978-07-10
IT1098670B IT1098670B (it) 1985-09-07

Family

ID=6013631

Family Applications (1)

Application Number Title Priority Date Filing Date
IT25515/78A IT1098670B (it) 1977-07-11 1978-07-10 Procedimento per la fabbricazione di elementi semiconduttori

Country Status (7)

Country Link
JP (1) JPS5419358A (it)
BR (1) BR7804249A (it)
CH (1) CH629336A5 (it)
DE (1) DE2731221A1 (it)
FR (1) FR2397717A1 (it)
GB (1) GB1604308A (it)
IT (1) IT1098670B (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57184597U (it) * 1981-05-20 1982-11-24
DE3211391A1 (de) * 1982-03-27 1983-09-29 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen einer halbleiteranordnung
DE3435138A1 (de) * 1984-09-25 1986-04-03 Siemens AG, 1000 Berlin und 8000 München Verbesserung zu einem verfahren zum vereinzeln von halbleiter-bauelementen, die durch brechen aus halbleiter-wafern gewonnen sind
DE3524301A1 (de) * 1985-07-06 1987-01-15 Semikron Gleichrichterbau Verfahren zum herstellen von halbleiterelementen
JPS63108706A (ja) * 1986-10-27 1988-05-13 Toshiba Corp 半導体装置の製造方法
JP5903287B2 (ja) * 2012-01-31 2016-04-13 新電元工業株式会社 半導体素子の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4860871A (it) * 1971-11-30 1973-08-25
JPS4976469A (it) * 1972-11-27 1974-07-23
US3972113A (en) * 1973-05-14 1976-08-03 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices

Also Published As

Publication number Publication date
JPS5419358A (en) 1979-02-14
CH629336A5 (en) 1982-04-15
IT1098670B (it) 1985-09-07
GB1604308A (en) 1981-12-09
BR7804249A (pt) 1979-04-10
DE2731221A1 (de) 1979-02-01
FR2397717A1 (fr) 1979-02-09

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