IT8026721A0 - Metodo per fabbricare un transistor con un profilo ideale delle impurita della base. - Google Patents

Metodo per fabbricare un transistor con un profilo ideale delle impurita della base.

Info

Publication number
IT8026721A0
IT8026721A0 IT8026721A IT2672180A IT8026721A0 IT 8026721 A0 IT8026721 A0 IT 8026721A0 IT 8026721 A IT8026721 A IT 8026721A IT 2672180 A IT2672180 A IT 2672180A IT 8026721 A0 IT8026721 A0 IT 8026721A0
Authority
IT
Italy
Prior art keywords
transistor
manufacturing
impurity profile
base impurity
ideal base
Prior art date
Application number
IT8026721A
Other languages
English (en)
Other versions
IT1150096B (it
Inventor
Billy Lee Crowder
Randall Duane Isaac
Tak Hung Ning
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT8026721A0 publication Critical patent/IT8026721A0/it
Application granted granted Critical
Publication of IT1150096B publication Critical patent/IT1150096B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
IT26721/80A 1979-12-28 1980-12-18 Metodo per fabbricare un transistor con un profilo ideale delle impurita della base IT1150096B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1979/001137 WO1981001911A1 (en) 1979-12-28 1979-12-28 Method for achieving ideal impurity base profile in a transistor

Publications (2)

Publication Number Publication Date
IT8026721A0 true IT8026721A0 (it) 1980-12-18
IT1150096B IT1150096B (it) 1986-12-10

Family

ID=22147840

Family Applications (1)

Application Number Title Priority Date Filing Date
IT26721/80A IT1150096B (it) 1979-12-28 1980-12-18 Metodo per fabbricare un transistor con un profilo ideale delle impurita della base

Country Status (6)

Country Link
EP (1) EP0042380B1 (it)
JP (1) JPS6410951B2 (it)
CA (1) CA1160363A (it)
DE (1) DE2967588D1 (it)
IT (1) IT1150096B (it)
WO (1) WO1981001911A1 (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4536950A (en) * 1983-02-10 1985-08-27 Matsushita Electric Industrial Co., Ltd. Method for making semiconductor device
US4912053A (en) * 1988-02-01 1990-03-27 Harris Corporation Ion implanted JFET with self-aligned source and drain
US5204276A (en) * 1988-12-06 1993-04-20 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JPH02153534A (ja) * 1988-12-06 1990-06-13 Toshiba Corp 半導体装置の製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3083441A (en) * 1959-04-13 1963-04-02 Texas Instruments Inc Method for fabricating transistors
US3389023A (en) * 1966-01-14 1968-06-18 Ibm Methods of making a narrow emitter transistor by masking and diffusion
US3432920A (en) * 1966-12-01 1969-03-18 Rca Corp Semiconductor devices and methods of making them
US3489622A (en) * 1967-05-18 1970-01-13 Ibm Method of making high frequency transistors
FR1569872A (it) * 1968-04-10 1969-06-06
US3717507A (en) * 1969-06-19 1973-02-20 Shibaura Electric Co Ltd Method of manufacturing semiconductor devices utilizing ion-implantation and arsenic diffusion
US3886569A (en) * 1970-01-22 1975-05-27 Ibm Simultaneous double diffusion into a semiconductor substrate
NL7116688A (it) * 1970-12-09 1972-06-13
US3753807A (en) * 1972-02-24 1973-08-21 Bell Canada Northern Electric Manufacture of bipolar semiconductor devices
US3856578A (en) * 1972-03-13 1974-12-24 Bell Telephone Labor Inc Bipolar transistors and method of manufacture
US3940288A (en) * 1973-05-16 1976-02-24 Fujitsu Limited Method of making a semiconductor device
US3880676A (en) * 1973-10-29 1975-04-29 Rca Corp Method of making a semiconductor device
US4066473A (en) * 1976-07-15 1978-01-03 Fairchild Camera And Instrument Corporation Method of fabricating high-gain transistors
US4115797A (en) * 1976-10-04 1978-09-19 Fairchild Camera And Instrument Corporation Integrated injection logic with heavily doped injector base self-aligned with injector emitter and collector
US4157269A (en) * 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques
US4168999A (en) * 1978-12-26 1979-09-25 Fairchild Camera And Instrument Corporation Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques

Also Published As

Publication number Publication date
IT1150096B (it) 1986-12-10
EP0042380A4 (en) 1983-04-18
JPS6410951B2 (it) 1989-02-22
DE2967588D1 (en) 1986-04-24
EP0042380B1 (en) 1986-03-19
CA1160363A (en) 1984-01-10
EP0042380A1 (en) 1981-12-30
WO1981001911A1 (en) 1981-07-09
JPS56501585A (it) 1981-10-29

Similar Documents

Publication Publication Date Title
EP0036867A4 (en) Double cavity semiconductor chip carrier.
BE849751A (fr) Procede de fabrication d'un document
BE848345A (fr) Procede de fabrication d'un dispositif a semi-conducteurs,
IT8125693A0 (it) Metodo di fabbricazione di un dispositivo semiconduttore.
BE853547A (fr) Procede de fabrication de transistors a effet de champ
IT7823833A0 (it) Processo di fabbricazione di dispositivi semiconduttori.
GB2054265B (en) Manufacturing emitters by diffusion from polysilicon
FR2353362A1 (fr) Procede de fabrication de pistons avec canal annulaire
NL7612883A (nl) Halfgeleiderinrichting, en werkwijze ter ver- vaardiging daarvan.
IT8121369A0 (it) Metodo di fabbricazione di un dispositivo semiconduttore.
GB2010580B (en) Method for manufacturing a semiconductor device
IT1024956B (it) Procedimento per la fabbricazione di un dispositivo semiconduttone
IT1129686B (it) Metodo di fabbricazione di acciaio
IT7826098A0 (it) Processo per la fabbricazione di dispositivi semiconduttori.
FR2307437A1 (fr) Procede de fabrication de cadres-supports de conducteurs metalliques
DK134394B (da) Fremgangsmåde til fremstilling af et kontaktlegeme.
IT8121861A0 (it) Profilatrice e procedimento per la fabbricazione di un profilo.
IT7831287A0 (it) Metodo e disposizione per la fabbricazione di confezioni.
IT8020125A0 (it) Dispositivo a semicondutture.
IT1150096B (it) Metodo per fabbricare un transistor con un profilo ideale delle impurita della base
BE854834A (fr) Procede de fabrication de rails a caracteristiques ameliorees
IT8221430A0 (it) Procedimento per la fabbricazione di un dispositivo a semiconduttori.
IT1089299B (it) Procedimento per fabbricare un dispositivo semiconduttore
PL209131A1 (pl) Sposob wytwarzania zwiazkow trojpierscieniowych z atomem azotu w pozycji wezlowej
IT8023183A0 (it) Dispositivo di illuminazione delle tastiere.